IKA SMRA + MRA, User Manual

Page: 26 / 40

SMRA - SSI and BiSS
DATA
When you need to write in a register (
RW
= “01”), it allows to set the value to
be written in the register (transmitted by the Master to the Slave).
When you need to read from a register (
RW
= “10”), it shows the value read in
the register (transmitted by the Slave to the Master).
It is 8-bit long.
Data bit structure:
bit 7 … … 0
MSB … … LSB
CRC
Correct transmission control (inverted output). Cyclical Redundancy Checking is
an error checking which is the result of a “Redundancy Checking” calculation
performed on the message contents. This is intended to check whether the
transmission has been performed properly. It is 4-bit long.
Polynomial: X
4 +X 1 +1 (binary: 10011)
Logic circuit
MAN SMRA SSI_BiSS E 1.4.odt 6 - BiSS C-mode interface 26 of 40
1st
stage
2nd
stage
3rd
stage
4th
stage
X 0
X
1
X
2
X
3
Input Data (starts from MSB)