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AL4142
Remote I/O module 16 DI
54
11.1.1.5 Block Configuration (400 - 408)
Register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
400
X8:
DI2
INV
X8:
DI1
INV
X7:
DI2
INV
X7:
DI1
INV
X6:
DI2
INV
X6:
DI1
INV
X5:
DI2
INV
X5:
DI1
INV
X4:
DI2
INV
X4:
DI1
INV
X3:
DI2
INV
X3:
DI1
INV
X2:
DI2
INV
X2:
DI1
INV
X1:
DI2
INV
X1:
DI1
INV
401
X8:
DI2
HL
X8:
DI1
HL
X7:
DI2
HL
X7:
DI1
HL
X6:
DI2
HL
X6:
DI1
HL
X5:
DI2
HL
X5:
DI1
HL
X4:
DI2
HL
X4:
DI1
HL
X3:
DI2
HL
X3:
DI1
HL
X2:
DI2
HL
X2:
DI1
HL
X1:
DI2
HL
X1:
DI1
HL
402
reserved
X8:
DIS
X7:
DIS
X6:
DIS
X5:
DIS
X4:
DIS
X3:
DIS
X2:
DIS
X1:
DIS
403
reserved
X8:
DIR
X7:
DIR
X6:
DIR
X5:
DIR
X4:
DIR
X3:
DIR
X2:
DIR
X1:
DIR
404
reserved
X8:
RST
MC
OV
X7:
RST
MC
OV
X6:
RST
MC
OV
X5:
RST
MC
OV
X4:
RST
MC
OV
X3:
RST
MC
OV
X2:
RST
MC
OV
X1:
RST
MC
OV
405
reserved
X8:
RST
MC
UV
X7:
RST
MC
UV
X6:
RST
MC
UV
X5:
RST
MC
UV
X4:
RST
MC
UV
X3:
RST
MC
UV
X2:
RST
MC
UV
X1:
RST
MC
UV
406
reserved
X8:
RST
BC
OV
X7:
RST
BC
OV
X6:
RST
BC
OV
X5:
RST
BC
OV
X4:
RST
BC
OV
X3:
RST
BC
OV
X2:
RST
BC
OV
X1:
RST
BC
OV
407
reserved
X8:
RST
BC
UV
X7:
RST
BC
UV
X6:
RST
BC
UV
X5:
RST
BC
UV
X4:
RST
BC
UV
X3:
RST
BC
UV
X2:
RST
BC
UV
X1:
RST
BC
UV
408
reserved
X8:
RST
CT
X7:
RST
CT
X6:
RST
CT
X5:
RST
CT
X4:
RST
CT
X3:
RST
CT
X2:
RST
CT
X1:
RST
CT
Legend:
• DI1 INV
Pin 4: signal inversion
1 BIT
• 0x0: do not invert (default)
• 0x1: invert
• DI2 INV
Pin 2: signal inversion
1 BIT
• 0x0: do not invert (default)
• 0x1: invert
• DI1 HL
Pin 4: Signal level to be maintained
1 BIT
• 0x0: LOW
• 0x1: HIGH (default)
• DI2 HL
Pin 2: Signal level to be maintained
1 BIT
• 0x0: LOW
• 0x1: HIGH (default)
• DIS
Disable Counter: disable main c batch
counter
1 BIT
• 0x0: no action (default)
• 0x1: disable main and batch counter
• DIR
Counter Direction: Set counting direction (valid
only for counter mode CTDIR)
1 BIT
• 0x0: up (default)
• 0x1: down
• RST MC OV
Reset Main Counter Overflow: Reset counter
event overflow of the main counter
1 BIT
• 0x0: no action (default)
• 0x1: Rest overflow event
• RST MC UV
Reset Main Counter Underflow: Reset counter
event underflow of the main counter
1 BIT
• 0x0: no action (default)
• 0x1: Reset underflow event
• RST BC OV
Reset Batch Counter Overflow: Reset counter
event overflow of the batch counter
1 BIT
• 0x0: no action (default)
• 0x1: Rest overflow event
• RST BC UV
Reset Batch Counter Underflow: Reset counter
event underflow of the batch counter
1 BIT
• 0x0: no action (default)
• 0x1: Reset underflow event
• RST CT
Reset main counter and batch counter to initial
value
1 BIT
• 0x0: no action (default)
• 0x1: reset main + batch counter and
counter events to overflow/underflow