QUICK START GUIDE
EPC – THE LEADER IN GaN TECHNOLOGY |
| COPYRIGHT 2019 | | 2
EPC9034
QUICK START PROCEDURE
The half bridge development board EPC9034 is easy to set up as buck or
boost converter. Refer to figure 2 for buck converter configuration and
measurement setup, and figure 3 for boost converter setup, and follow the
procedure below:
Buck converter configuration
1. With power off, connect the input power supply bus to V
IN
(J5, J6) and
ground / return to GND.
2. With power off, connect the switch node (SW) of the half bridge to your
circuit as required (half bridge configuration). Or use the provided pads
for inductor (L
1
) and output capacitors (C
out
), as shown in figure 2 with a
DC load connected across V
OUT
and GND.
3. With power off, connect the gate drive supply to V
DD
(J1, Pin-1) and
ground return to GND (J1, Pin-2 indicated on the bottom side of the
board).
4. With power off, connect the input PWM control signal to PWM1 (J2,
Pin-1) and ground return to any of GND J2 pins indicated on the bottom
side of the board.
5. Turn on the gate drive supply – make sure the supply is between 7.5 V
and 12 V.
6. Turn on the controller / PWM input source.
7. Making sure the intial input supply voltage is 0 V, turn on the power
and slowly increase the voltage to the required value (do not exceed
the absolute maximum voltage). Probe switching node to see switching
operation.
8. Once operational, adjust the PWM control, bus voltage, and load within
the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
EPC9034 development board
Front view
Table 1: Performance Summary (T
A
= 25°C) EPC9034
Symbol
Parameter
Conditions
Min
Max
Units
V
DD
Gate Drive Input Supply Range
7
12
V
V
IN
Bus Input Voltage Range
(1)
64
(1)
V
I
OUT
Switch Node Output Current
(2)
35
(2)
A
V
PWM
PWM Logic Input Voltage
Threshold
Input ‘High’
Input ‘Low’
3.5
0
6
1.5
V
V
V
SW
Switch-node Voltage
64
(1)
Minimum ‘High’ State Input
Pulse Width
V
PWM
rise and fall
time < 10ns
50
ns
Minimum ‘Low’ State Input
Pulse Width
(3)
V
PWM
rise and fall
time < 10ns
100
(3)
ns
(1) Maximum input voltage depends on inductive loading, maximum switch node ringing
must be kept under 80 V for EPC2021.
(2) Maximum current depends on die temperature – actual maximum current with be
subject to switching frequency, bus voltage and thermal cooling.
(3) Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
DESCRIPTION
The EPC9034 development board is a 80 V maximum device voltage, 35 A
maximum output current, half bridge with onboard gate drives, featuring
the EPC2021 enhancement mode (eGaN®) field effect transistor (FET).
The purpose of this development board is to simplify the evaluation
process of the EPC2021 eGaN FET by including all the critical components
on a single board that can be easily connected into the majority of
existing converter topologies.
The EPC9034 development board measures 2” x 2” and contains two
EPC2021 eGaN FETs in a half bridge configuration using the Texas
Instruments LMG1205 gate driver. The board also contains all critical
components and the layout supports optimal switching performance.
There are also various probe points to facilitate simple waveform
measurement and efficiency calculation. A block diagram of the circuit
is given in figure 1.
For more information on the EPC2021 please refer to the datasheet
available from EPC at
. The datasheet should be read in
conjunction with this quick start guide.
Back view
