QUICK START GUIDE
EPC – THE LEADER IN GaN TECHNOLOGY |
| COPYRIGHT 2019 | | 2
EPC9013
DESCRIPTION
The EPC9013 development board features the 100 V EPC2001C enhance-
ment mode (eGaN®) field effect transistor (FET) operating up to a
35 A maximum output current with four half bridges in parallel and a
single onboard gate drive. The purpose of this development board is
to simplify the evaluation process of the EPC2001C eGaN FET for high
current operation by including all the critical components on a single
board that can be easily connected into any existing converter.
The EPC9013 development board is 2” x 2” and features eight EPC2001C
eGaN FETs using the uPI Semiconductor uP1966A gate driver.
The development board configuration is recommended for high
current applications. The board contains all critical components and
the printed circuit board (PCB) layout is designed for optimal switching
performance. There are also various probe points to facilitate simple
waveform measurement and evaluate eGaN FET efficiency. A complete
block diagram of the circuit is given in Figure 1.
For more information on the EPC2001C please refer to the datasheet
available from EPC at
. The datasheet should be read in
conjunction with this quick start guide.
Table 1: Performance Summary (T
A
= 25°C) EPC9013
Symbol
Parameter
Conditions
Min Max Units
V
DD
Gate Drive Input Supply Range
7
12
V
V
IN
Bus Input Voltage Range
(1)
70
V
V
OUT
Switch Node Output Voltage
100
V
I
OUT
Switch Node Output Current
(2)
200 LFM
35
A
V
PWM
PWM Logic Input Voltage
Threshold
Input ‘High’
Input ‘Low’
3.5
0
6
1.5
V
V
Minimum ‘High’ State Input
Pulse Width
V
PWM
rise and
fall time < 10ns
60
ns
Minimum ‘Low’ State Input Pulse
Width
(3)
V
PWM
rise and
fall time < 10ns 100
ns
(1) Assumes inductive load, maximum current depends on die temperature – actual maxi-
mum current will be subject to switching frequency, bus voltage and thermals.
(2) Maximum current depends on die temperature – actual maximum current with be
subject to switching frequency, bus voltage and thermal cooling.
(3) Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
QUICK START PROCEDURE
Development board EPC9013 is easy to set up to evaluate the
performance of the EPC2001C eGaN FET. Refer to Figure 2 for proper
connect and measurement setup and follow the procedure below:
1. With power off, connect the input power supply bus to +V
IN
(J5, J6) and
ground / return to –V
IN
(J7, J8).
2. With power off, connect the switch node of the half bridge OUT (J3,
J4) to your circuit as required.
3. With power off, connect the gate drive input to +V
DD
(J1, Pin-1) and
ground return to –V
DD
(J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM (J2,
Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V
and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the
absolute maximum voltage of 100 V on V
OUT
).
7. Turn on the controller / PWM input source and probe switching
node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control
within the operating range and observe the output switching
behavior, efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE.
When measuring the high frequency content switch node (OUT), care must
be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip on the switch node (designed for this purpose) and grounding the
probe directly across the GND terminals provided. See Figure 3 for proper scope probe
technique.
For information about measurement techniques, please review the how to GaN series:
HTG09- Measurement
http://epc-co.com/epc/DesignSupport/TrainingVideos/HowtoGaN/
EPC9013 development board
Figure 1: Block diagram of EPC9013 development board
Lev
el shif
t
V
DD
V
IN
Q
1
Q
2
C
Bypass
PWM
GND
Gate drive
regulator
Gate driver
Output
PGND
Logic and
dead-time
adjust