59
Appendix E.
Signal mapping of LVDS
(18bit LVDS mapping table )
(R0)
(B2)
(R1)
(B3)
(R2)
(B4)
(R3)
(B5)
(R4)
HSYNC
(R5)
VSYNC
(G0)
1
st
LVDS
(data0 output - )
(data0 )
DE
1
st
LVDS
(data2 output - )
(data2 )
(G1)
(G2)
(G3)
(G4)
(G5)
(B0)
(B1)
1
st
LVDS
(data1 output - )
(data1 )
DCLK
1
st
LVDS
(clock output - )
(clock )
(36bit LVDS mapping table )
(RA0)
(BA2)
(RA1)
(BA3)
(RA2)
(BA4)
(RA3)
(BA5)
(RA4)
HSYNC
(RA5)
VSYNC
(GA0)
1
st
LVDS
(data0 output - )
(data0 )
DE
1
st
LVDS
(data2 output - )
(data2 )
(GA1)
(GA2)
(GA3)
(GA4)
(GA5)
(BA0)
(BA1)
1
st
LVDS
(data1 output - )
(data1 )
DCLKA
1
st
LVDS
(clock output - )
(clock )
Summary of Contents for JUKI-C400 Series
Page 10: ...10 Layout JUKI C400 Series...
