IEI Technology ECK-161B, User Manual

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ECK-161B Embedded System
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250 MHz core render clock and 200 MHz core display clock at 1.05 V
core voltage
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Supports TV-Out, CRT and SDVO
DMI
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Chip-to-chip interface between (G)MCH and ICH
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Configurable as x2 or x4 DMI lanes
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DMI lane reversal support
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32-bit downstream address
Power Management
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ACPI S0, S3, S4, S5
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CPU States C0, C1, C2, C3, C4 states
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Rapid Memory Power Mgmt
3.2.3 Intel ICH7-M Southbridge Chipset
The Intel® ICH7-M Southbridge chipset comes with the following features:
PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations
(supports up to six Req/Gnt pairs)
ACPI Power Management Logic support
Enhanced DMA controller, interrupt controller, and timer functions
Integrated Serial ATA host controller with independent DMA operation on two
ports and AHCI
Integrated IDE controller supports Ultra ATA 100/66/33
USB host interface with support for six USB ports; four UHCI host controller;
one EHCI high-speed USB 2.0 Host controller
Integrated Intel® PRO 82573E GbE controller
Supports Audio Codec ’97, Revision 2.3 Specification
Supports Intel® High Definition Audio
Low Pint Count (LPC) interface
Firmware Hub (FWH) interface support
Serial Peripheral Interface (SPI) support