Industrial Electronic Engineers, Inc.
SIZE
A
CODE IDENT NO.
05464
S03858–06–0205
Van Nuys, California
SCALE N/A
REV C
SHEET 7
2.2
LCD Controller
The LCD Controller includes all of the circuitry necessary to take parallel input data and create the necessary
control functions and characters. The block diagram of the controller is shown in Figure 2 below. The
remaining subparagraphs of Section 2 describe the major function blocks.
DB4–DB7
E
R/W
RS
DB0–DB3
4
4
I/O Buffer
Instruction
Decoder
Instruction
Register (IR)
Data
Register (DR)
Busy
Flag
I/O Buffer
8
Character
Generator
RAM
(CG RAM)
512 Bits
Cursor Blink
Control Circuit
Display Data
RAM
(DD RAM)
80x8 bits
8
8
8
Character
Generator
ROM
(CG ROM)
7200 Bits
8
7
7
Timing Generation
Circuit
Address
Counter (AC)
7
Common Signal
Driver
16–bit Shift
Register
3
16
16
CL1
CL2
M
Parallel/Serial Data
Conversion Circuit
(Parallel Data –Serial Data)
40–bit Latch
Circuit
Segment Signal
Driver
40–bit Shift Register
Seg1–Seg40
Com1–Com16
D
5
5
40
Figure 2
LCD Controller Block Diagram
2.2.1
Instruction Register (IR)
The IR stores instruction codes such as display clear and cursor shift, and address information of the display
data RAM (DD RAM) and character generator RAM (CG RAM). The IR can be written from the MPU, but not
read.
2.2.2
Data Register (DR)
The DR temporarily stores data to be written into or read from the DD RAM or the CG RAM.
2.2.3
Busy Flag
When the Busy Flag is a "1", the module is in an internal operating mode and ignores any additional instructions
(Refer to Read Busy Flag and Address instruction).
2.2.4
Address Counter (AC)
The AC determines the address of the DD RAM or CG RAM in which new data is stored. After writing into (or
reading from) the DD RAM or CG RAM, the AC is incremented or decremented as defined by the
