REVISION A 05/13/15
9
VERSACLOCK
®
5 - 5P49V5935/33 Evaluation Boards
Signal Termination Options
Termination options for OUTPUT1 – 4 in the evaluation board are displayed in Figure 8. The termination circuits are designed to
optionally terminate the output clocks in LVPECL, LVDS, LVCMOS and HCSL signal types by populating (or not-populating)
some resistors. DC or AC coupling of these outputs are also supported.
Tables1 – 2, below, tabulates component installations to support LVPECL, HCSL, LVCMOS and LVDS signal types for OUTPUT1
– 4, respectively. Please note that by doing so, the output signals will be measured and terminated by an oscilloscope with a 50
internal termination.
Figure 8. Output Termination Options
