12. Serial RapidIO Registers > RapidIO Error Management Extension Registers
285
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.7
RapidIO Error Management Extension Registers
This section describes the registers in the Extended Features block (EF_ID = 0x0007), which is defined
in Part VIII of the RapidIO specification. These registers enable an external processing element to
manage the error status and reporting for a processing element.
These registers are reset by the HARD_RST_b reset input signal, as well as when the Tsi578 performs
a self-reset. The registers within a port are also reset by a
. For more information on Tsi578
reset implementation and behavior, see
“Clocks, Resets and Power-up Options” on page 205
. It is
possible to override reset values of writable fields using the I
2
C register loading capability on boot.
Refer to
for more information on the use of I
2
C controller register loading
capability.
The Logical/Transport Error Detect registers are not required for a switch. However, a switch’s register
bus access errors and transport errors are reported per port in bit 0 of the
. The port’s capture registers contain error information.
All registers are 32-bits and aligned to a 32-bit boundary
Ti
p
Not all Error Management Extension registers are supported in the Tsi578.
When an individual port is powered down, the RapidIO Error Management Extension
Registers are read only and return 0.
Software must not write to reserved addresses, and reserved bits in the RapidIO Error
Management Extension registers should be written with zero.
Table 38: Error Management Registers
Port
Offset
Description
All
0x1000
General Error Management capability registers
SP0
0x1040
1x/4x Serial port
SP1
0x1080
1x Serial port
SP2
0x10C0
1x/4x Serial port
SP3
0x1100
1x Serial port
SP4
0x1140
1x/4x Serial port
SP5
0x1180
1x Serial port
SP6
0x11C0
1x/4x Serial port
SP7
0x1200
1x Serial port
SP8
0x1240
1x/4x Serial port
