10. Clocks, Resets and Power-up Options > Resets
210
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
Timing of HARD_RST_b
The Tsi578 requires the following timing for the HARD_RST_b signal:
•
HARD_RST_b must be asserted for a minimum of 1 millisecond (ms).
•
Tsi578 comes out of reset within 1 ms after HARD_RST_b is de-asserted after assertion.
— A boot load from the I2C EEPROM will delay when the device becomes ready for RapidIO
traffic on the ports. See
“Boot Load Sequence” on page 166
for more information on boot
loading and the time implications.
10.2.1.3
RapidIO Reset Requests
The Tsi578 responds to Reset Request Control Symbols as defined by the
RapidIO Interconnect
Specification (Revision 1.3)
.
Self Reset
When a reset request occurs, the Tsi578’s response is controlled by the
. By default, the Tsi578 resets itself. A self-reset occurs when four link-request/reset-device
control symbols are received in a row (without any other intervening packets or control symbols,
except status control symbols) and the SELF_RST field in the
is set. When a self-reset is performed, it is not necessary to drive the HARD_RST_b input
signal. The SW_RST_b signal remains asserted for the duration of the self reset, which is at least four
P_CLK clock cycles.
If the SELF_RST field is not set an interrupt signal is asserted (if RCS_INT_EN is also set in the
“RapidIO Port x Mode CSR” on page 310
).
System Control of Resets
Self-reset of the Tsi578 may not be sufficient in systems which require other components to be reset at
the same time as the Tsi578. The Tsi578 supports system control of resets in two ways. First, the Tsi578
can assert the INT_b interrupt so that a local processor can trigger a reset through the Tsi578’s
HARD_RST_b pin. For this design to work, reset interrupts must be enabled in the
“Global Interrupt Enable Register” on page 390
Secondly, if interrupts are not suitable for reset functionality in a system, it is possible to use the
SW_RST_b output pin. When the Tsi578 has received a reset request, the SW_RST_b output pin is
asserted until the reset request status is cleared in the port that received it. The SW_RST_b output pin
can be used as an input to a reset controller to trigger the start of a system reset. If self-reset is not
enabled, SW_RST_b remains asserted until the device is reset through the input reset pin
HARD_RST_b or until the interrupt bit is cleared for the port that received the reset message. If
self-reset is enabled, SW_RST_b is asserted for the duration of the reset, which is at least four P_CLK
clock cycles.
When the Tsi578 is in reset, the INT_b pin is not asserted.
