7. I
2
C Interface > Events versus Interrupts
177
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
7.11
Events versus Interrupts
Interrupts are generated by I
2
C events.
shows the design of the event and interrupt logic. A
single interrupt status bit may be derived from one or more events. The event registers provide control
over the individual events that in turn produce the interrupt status. In the diagram, the shaded boxes
represent virtual registers. These registers behave correctly when read or written, but can be
constructed from combinational logic as opposed to flip-flops. Whether a register is virtual or not is
inconsequential to their behavior from a software perspective. The distinction is shown only for
exactness.
A new event is set in the
when an event is asserted in the logic, or when a 1
is written to the register (or to the related interrupt bit in the
). New events
are ored with the I2C_SNAP_EVENT register to create the virtual I2C_EVENT register. A snapshot
operation occurs when the
is read. As a result of the snapshot, the new
event register is “copied” to the snapshot register by oring the new events into the current snapshot
state, then clearing the new event register. Each event is anded with the corresponding enable bit in the
, and then ored with any other enabled events that are related to a single
interrupt status bit. The combined event state becomes the interrupt status bit in the Interrupt Status
Register, and is then anded with the corresponding enable in the
the enabled interrupt status bits are then ored together to become the single interrupt signal to the
Interrupt Controller.
The new event and snapshot registers separate events that occurred prior to a read of the interrupt status
register from those that occur during or after the read. When a 1 is written to the interrupt status register
to clear an interrupt, all related events that are enabled are cleared in the snapshot register. Since events
are copied to the snapshot register only when the interrupt status register is read, the read must be
completed first for the write 1 to clear to have effect. If no new events have occurred, this
write-1-to-clear de-asserts the interrupt status. If a new event has occurred, the event remains set in the
new event register, so the interrupt status remains set.
For control purposes, software can read and clear the snapshot event bits directly, allowing individual
events to be cleared while leaving any new events intact. Software can also select to read or clear
events using the new event register. Reading the event register shows the “or” of the new and snapshot,
and thus shows whether an event is asserting. Writing a 1 to an event bit clears both the snapshot and
new events register bits, thus clearing out the event entirely, unless that event happens to be asserting
again on the same cycle the clear is completed, thus setting it again.
As long as all event enables are set (the reset state), then the behavior is logical (see
).
