IDT Tsi578, User Manual

Page: 148 / 527

7. I
2
C Interface > Tsi578 as I
2
C Master 148
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
Figure 31: Software-initiated Master Transactions
P
Shaded = Response From External Device A = Ack N = Nack S = Start P = Stop R = Restart
S PerAdrMsb PerAdrLsb WriteData 7 Bit Wr(0)
Slave Address Peripheral Address Data Written to Device
WriteData A A A A A WriteData WriteData A A
Arbitration Loss
pa_size=2 pa_size>=1
size=4 size>=3
size>=2 size>=1
Write Transaction (WRITE=1)
From DEV_ADDR From PADDR From I2C_MST_WDATA
P
S PerAdrMsb PerAdrLsb
ReadData
7 Bit Wr(0)
Slave Address Peripheral Address
Data Read from Device
ReadData
A
A A
A A
ReadData ReadData N A
Arbitration Loss pa_size=2 pa_size>=1
size=4 size>=3
size>=2 size>=1
From DEV_ADDR
From PADDR
To I2C_MST_RDATA
Read Transaction (WRITE* = 0, PA_SIZE* > 0)
P S ReadData 7 Bit Rd(1)
Slave Address
Data Read from Device
ReadData A A A ReadData ReadData N A
Arbitration Loss
size=4 size>=3
size>=2 size>=1
From DEV_ADDR To I2C_MST_RDATA
Read Transaction (WRITE=0, PA_SIZE = 0)
R 7 Bit Rd(1)
Slave Address
A
From DEV_ADDR
Readdress for Read
Note : WRITE resides in the “I
2
C Master Control Register” , while PA_SIZE
resides in the “I
2
C Master Configuration Register” .