IDT TSI384, User Manual

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3. Data Path 41
Tsi384 User Manual
May 5, 2014
Integrated Device Technology
www.idt.com
Every 512-byte buffer also consists of 32-byte sub-sections in PCI mode and 128-byte subsections in
PCI-X mode. In PCI mode, the Tsi384 allows the delayed response data transfer to the requester only if
the programmed number of 32-byte chunks of data are accumulated in the data buffer (see
CPL_INIT_COUNT in
“PCI Miscellaneous Control and Status Register” ). In PCI-X mode, the Tsi384
initiates split completion transactions only on 128-byte boundaries. However, read completions with
byte counts larger than 128 bytes can be returned to the PCI-X bus provided the data is available in the
buffer.
The Tsi384 continues to try the outstanding split completion transactions in a round-robin fashion, even
if the current split transaction received a retry or abort response.
While each request queue entry has up to 512 bytes of buffer space, in order to keep data flowing
efficiently, the 128-byte sub-sections are reused as needed when they are emptied. This means that
when the PCIe and PCI/X Interfaces are operating at similar frequencies and there is little bus
contention, long transfers can proceed without disconnection after the initial latency needed to fill the
first 128-byte sub-section. For large transfers when the PCI/X bus is operating at low frequency,
disconnections can occur on every 128 bytes as the 512-byte buffer becomes empty.
This buffer contains an eight-deep request queue that stores address and command information for PCI
delayed transactions (reads/writes) and PCI-X split transactions (reads/writes). This handles
non-posted transactions that originate on the PCI/X Interface and are destined to devices on the PCIe
Interface.
3.3.1.1 Non-posted Write Buffer
The Tsi384 supports one non-posted write transaction. Similar to read requests, its request information
is stored in one of the eight request queue entries, and its data is stored in a 32-bit register. Non-posted
write requests are forwarded onto the PCIe Core in two PCIe clock cycles. Request information is
forwarded in the first cycle, while 32-bit data is forwarded in the second cycle.
3.3.2 Upstream Posted Buffer
The upstream posted buffer is a FIFO of size 4-KB that stores memory write transactions that originate
on the PCI/X Interface and are destined to devices on PCIe Interface. The Tsi384 completes the posted
transactions on the originating bus before forwarding them to the PCIe Interface. Unlike the read
buffers, the amount of space assigned to each transaction is dynamic. A single transaction can use
4-KB of buffer space. The Tsi384 translates all types of memory write transactions from the PCI/X
Interface to memory write requests on the PCIe Interface. The Tsi384 terminates a new transaction with
retry and an active transaction with disconnect if sufficient buffer space is not available.
The Tsi384 uses an 8-deep request FIFO to store the request information, including first and last
Dwords byte enables of the received transactions.
Memory write transactions can contain any or all invalid payload bytes, where as memory write and
invalidate (MWI) or memory write block command transactions carry all the valid payload bytes. The
Tsi384 decomposes the received transactions with non-contiguous byte enables on 32-byte boundaries
while writing into the request FIFO.
The PCI Core makes a request to the PCIe Core if one of the following conditions is met:
• All data bytes of the transaction are received and are stored in the data buffer