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1. Board Design

17

Tsi381 Evaluation Board User Manual

60E2000_MA001_03

Integrated Device Technology

www.idt.com

Three levels of reset are available: 

Cold reset – This reset is applied during power up. System (card edge) PCIe_PERSTn is muxed 
with the board’s reset controller. 

Warm reset – This reset is activated by a push-button reset on the board. 

Hot reset – This reset is activated by the in-band message sent by the root complex. No supporting 
hardware is necessary. 

1.8

Logic Analyzer Connectivity

The serial buses have Midbus pads (TMS818 probe) for visibility of SerDes lines using a 
pre-processor. Each probing pad provides access to the RX and TX segments of a x1 link.  

To access the PCI bus, a Nexus PCI interposer card can be used with Tektronix mictor cables. The card 
can be plugged into any PCI edge slot, or in-line with the device under test. 

Ti

p

For more information on cold, warm, and hot reset levels, see the “Resets, Clocking, and 
Initialization Options” chapter in the 

Tsi381 User Manual

Summary of Contents for Tsi381

Page 1: ...ek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2009 Integrated Device Technology Inc Tsi381 Evaluation Board User Manual 60E2000_MA001_0...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...Sequencing 13 1 4 4 System Power Design 13 1 4 5 PCI Vaux PCI Auxiliary Support 14 1 5 Clock Management 14 1 5 1 PCI 14 1 5 2 System Clock Distribution 15 1 6 Other Interfaces 15 1 6 1 JTAG Interface...

Page 4: ...Contents 4 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com 2 4 3 P1 x1 PCIe Finger Connector 31 2 5 LEDs 31 3 Bill of Materials 33...

Page 5: ...Design Guidelines PCI Express Base Specification Revision 1 1 PCI Express CEM Specification Revision 1 1 PCI Express to PCI PCI X Bridge Specification Revision 1 0 Acronyms Revision History 60E2000_MA...

Page 6: ...About this Document 6 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com...

Page 7: ...Clock Management on page 14 Other Interfaces on page 15 Hardware Reset on page 16 Logic Analyzer Connectivity on page 17 1 1 Overview The key features of the Tsi381 evaluation board include the follo...

Page 8: ...ard Block Diagram EEPROM Tsi381 3 3V PCI 32 bit Connector Slot 0 PCI Power Management PCI Express Card Edge X1 PCIe LA Probe JTAG Header ATX Connectors EEPROM 1x SerDes SMA Points SerDes Path Resistor...

Page 9: ...erating at 25 33 50 or 66 MHz 1 2 2 IDSEL Signals IDSEL signals are connected in the following order Slot 0 R A connector top slot 150 ohms to AD16 Device 0 Slot 1 150 ohms to AD17 Device 1 Slot 2 150...

Page 10: ...r chain continuity 1 4 Power Management 1 4 1 Power Regulation The evaluation board s power regulation is implemented as follows Digital 3 3V power supply available from DC DC regulator or ATX supply...

Page 11: ...are a maximum of 25W slot Current limits are included in Table 4 The usage of the 12V supply provides access to the full 25W available from the system to the board The PCIe pinout design includes more...

Page 12: ...tions summarize the power available for a single PCI card without external supply An efficiency of 85 is taken into account for switching regulators These limits can be exceeded in cases where the sys...

Page 13: ...following list is a functional summary of the power design 1 Sequencing control over the following rails 3 3V PCI 3 3V Tsi381 I O PCIe AVDD 1 2V Tsi381 Core PCIe VDD 2 ATX 20 pin connector override w...

Page 14: ...ports master and slave clocking for PCI Master When in master mode the Tsi381 generates the required PCI clock for all slots Slave When in slave mode an on board selectable 25 66 MHz clock generator i...

Page 15: ...iggler connection 1 6 2 EEPROM Interface A single EEPROM device socket is available for programming the Tsi381 s registers during startup The socket is in an 8 pin DIP format Tip For more information...

Page 16: ...wing list outlines the connections to GPIO External I O header J7 1 NC J7 2 GPIO0 J7 3 GPIO1 J7 4 GPIO2 J7 5 GPIO3 J7 6 Connected to ground LEDs D11 GPIO0 active led when driven low D1 GPIO1 active le...

Page 17: ...ssage sent by the root complex No supporting hardware is necessary 1 8 Logic Analyzer Connectivity The serial buses have Midbus pads TMS818 probe for visibility of SerDes lines using a pre processor E...

Page 18: ...1 Board Design 18 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com...

Page 19: ...the following Switches on page 19 Shunt Jumpers on page 24 Debug Headers on page 26 Connectors on page 29 LEDs on page 31 2 1 Switches 2 1 1 DIP Switches Switches S1 to S6 combine four small slide sw...

Page 20: ...2 Configurable Options 20 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com Figure 6 Switch Locations SW2 S3 S4 SW1 S5 S6 S1...

Page 21: ...Table 8 contains the clock frequency settings for S3 Table 7 S1 Settings Switch Number Description Default Setting On Off Setting 1 M66EN ON ON Connects M66EN to all cards OFF Forces M66EN high if S1...

Page 22: ...L is reference clock from connector J10 OFF Clock source for PLL is a 25 MHz oscillator 3 PLL select OFF ON PLL is bypassed OFF PLL is enabled External clock source is multiplied as per S3 setting 4 N...

Page 23: ...evaluation board is powered up with a stand alone ATX power supply SW2 is used to reset the evaluation board When pushing the reset button the board is reset the same way a PCIe system reset would res...

Page 24: ...Manual 60E2000_MA001_03 Integrated Device Technology www idt com 2 2 Shunt Jumpers Shunt jumpers control special features on the evaluation board see Figure 7 These jumpers are explained in the follow...

Page 25: ...On Off push button to enable the ATX power supply 2 2 2 J21 Shunt Jumper J21 is used to force the Tsi381 into a special debug mode The default setting for this jumper is ON Table 12 J6 Shunt Jumper Se...

Page 26: ...n Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com 2 3 Debug Headers Debug headers are used to connect to signals on the evaluation board This section provides header pinout...

Page 27: ...rated Device Technology www idt com 2 3 1 J22 Tsi381 JTAG Table 13 J22 Pin Assignment Pin Number Signal Assignment Pin Location 1 TDO 2 NC 3 TDI 4 3 3V 5 NC 6 3 3V 7 TCK 8 NC 9 TMS 10 NC 11 NC 12 GND...

Page 28: ...14 J23 Pin Assignment Pin Number Signal Assignment Pin Location 1 PCIE_RXD_EDG_P0 2 GND 3 PCIE_RXD_EDG_N0 4 PCIE_TXD_EDG_P0 5 GND 6 PCIE_TXD_EDG_N0 7 N C 8 GND 9 N C 10 N C 11 GND 12 N C 13 N C 14 GN...

Page 29: ...rable Options 29 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com 2 4 Connectors Figure 9 Board Connector Locations P1 J3 J2 Slot 0 J36 Slot 1 J1 Slot 2 J3...

Page 30: ...gnments are as per the PCI standard for 32 bit connectors 2 4 2 J3 ATX Power Connector A standard ATX power supply can be used to power up the board when used stand alone not plugged into a PCIe syste...

Page 31: ...001_03 Integrated Device Technology www idt com 2 4 3 P1 x1 PCIe Finger Connector The pin assignment for the finger connector is as per the PCIe standard Note that the JTAG signals TDI and TDO are con...

Page 32: ...2 Configurable Options 32 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com...

Page 33: ...CAPC0603 X5R CER SMT 0 1UF 10 25V 0603 5 C10 C62 C110 C140 C162 0402ZC103KAT2A 0402ZC103KAT2A AVX CAPC0402 X7R CER SMT 0 01UF 10 10V 0402 113 C17 21 C23 25 C38 C48 49 C52 C60 61 C63 65 C72 C105 C108...

Page 34: ...TINTED DIFFUSED 1 D9 B220A 13 F DIODES INC DIOSMA 2A SCHOTTKY DIODE RECTIFIER0 5VF 1 D10 S1B S1B FAIRCHILD DIOSMA GENERAL PURPOSE RECTIFIER 1 D23 LCDA15C 1 TC SEMTECH SOT143 TVSDIODEARRAY 1 F1 R154 01...

Page 35: ...3 5 R9 12 R209 ERJ 3GEYJ242V ERJ 3GEYJ242V PANASONIC RESC0603 RES SMT 2 4K OHM 0 1W 5 0603 18 R13 R52 ERJ 3EKF1001V ERJ 3EKF1001V PANASONIC RESC0603 RES SMT 1K OHM 0 1W 1 0603 R83 R86 87 R91 R93 R95 R...

Page 36: ...75 OHM 0 1W 1 0603 1 R121 ERJ 3GEYJ473V ERJ 3GEYJ473V PANASONIC RESC0603 RES SMT 47K OHM 0 1W 5 0603 2 R122 R138 WSL2010R1000FE A VISHAY RESC2010 RES SMT 0 100 OHM 0 5W 1 2010 CURRENTSENSE 1 R132 ERJ...

Page 37: ...65VTO5 5V 1 U5 SN74LVC1G14DBV T SN74LVC1G14DBV T TI SOT23 5 SINGLE SCHMITT TRIGGER INVERTER 1 U6 ICS87604AGI ICS87604AGILF IDT TSOP65P81 28 LOW VOLTAGE LOW SKEW 1 4 PCI PCI X ZERO DELAY CLOCK GENERATO...

Page 38: ...OS COMPARATOR R TO R INPUT OPEN DRAINOUTPUT 1 U33 EL7532IYZ INTERSIL TSSOP50P49 10 MONOLITHIC 2A STEP DOWN REGULATOR 1 5MHZ 2 6 5V IN 0 8 TO VIN OUT 2 Y1 2 HCM4925 000MAB JT HCM4925 000MAB J UT CITIZE...

Page 39: ...r products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any...

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