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59

Tsi310 User Manual

80B6020_MA001_05

4. Transaction

Ordering

This chapter discusses the following topics:

•

“Overview of Transaction Ordering” on page 59

•

“General Ordering Guidelines” on page 59

•

“Ordering Rules” on page 60

4.1

Overview of Transaction Ordering

To maintain data coherence and consistency, the Tsi310 complies with the ordering rules set
forth in the

PCI Local Bus Specification (Revision 2.2)

for the PCI mode and the

PCI-X

Addendum to PCI Local Bus Specification (Revision 1.0a)

for the PCI-X mode.

This chapter describes the ordering rules that control transaction forwarding across the Tsi310.
For more information on transaction ordering, see Appendix E of the

PCI Local Bus

Specification (Revision 2.2)

for the PCI mode and Section 8.4.4 of the

PCI-X Addendum to PCI

Local Bus Specification (Revision 1.0a)

for the PCI-X mode.

4.2

General Ordering Guidelines

Independent transactions on the primary and secondary buses have a relationship only when
those transactions cross the Tsi310.

The following general ordering guidelines govern transactions crossing the Tsi310:

•

Requests terminated with target retry can be accepted and completed in any order with
respect to other transactions that have been terminated with target retry. If the order of
delayed or split requests is important, the initiator should not start a second delayed or split
transaction until the first transaction has been completed. If more than one delayed or split
transaction is initiated, the initiator should repeat all retried requests, using some fairness
algorithm. Repeating a delayed or split transaction cannot be contingent upon the
completion of another delayed transaction; otherwise, a deadlock can occur.

•

Write transactions flowing in one direction have no ordering requirements with respect to
write transactions flowing in the opposite direction. The Tsi310 can accept posted write
transactions on both interfaces at the same time, and also can initiate posted write
transactions on both interfaces at the same time.

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Summary of Contents for Tsi310TM

Page 1: ...ek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2009 Integrated Device Technology Inc IDT Tsi310 PCI X Bridge User Manual 80B6020_MA001_0...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...6 Optional Features 23 1 2 7 Bus Arbitration 23 1 2 8 IEEE 1149 1 JTAG Port 23 1 3 Operation Overview 24 1 3 1 Supported Modes 24 1 3 2 Buffer Structure 24 1 3 3 Address Decoding 25 1 3 4 Bus Arbitrat...

Page 4: ...ty 48 3 5 Driver Impedance Selection 49 3 6 Reset Functions and Operations 50 3 6 1 Primary Reset 50 3 6 2 Secondary Reset 51 3 7 Bus Parking and Bus Width Determination 53 3 8 Power Management and Ho...

Page 5: ...dinate Bus Number Register 86 5 4 16 Secondary Latency Timer Register 87 5 4 17 I O Base Register 88 5 4 18 I O Limit Register 89 5 4 19 Secondary Status Register 90 5 4 20 Memory Base Register 92 5 4...

Page 6: ...7 PCI X ID Register 133 5 5 18 Next Capabilities Pointer Register 134 5 5 19 PCI X Secondary Status Register 135 5 5 20 PCI X Bridge Status Register 137 5 5 21 Secondary Bus Upstream Split Transaction...

Page 7: ...2 Excluding the Tsi310 from a JTAG Scan Ring 172 7 4 Instruction Register and Codes 173 7 5 Bypass Register 173 7 6 JTAG Device ID Register 174 7 7 Boundary Scan Register 174 7 7 1 Boundary Scan Regi...

Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...

Page 9: ...ration Transaction Address Formats 38 Figure 3 Programmable Pull up Circuit 48 Figure 4 De assertion of S_RST 52 Figure 5 Filter Requirements for P_VDDA and S_VDDA 161 Figure 6 Inductor L1 Impedance 1...

Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...

Page 11: ...als 151 Table 14 Secondary Interface Signals 154 Table 15 Strapping Pins and Other Signals 157 Table 16 Test Signals 160 Table 17 Power and Ground Connections 161 Table 18 Inductor L1 Characteristics...

Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...

Page 13: ...0B6020_MA001_04 Formal December 2004 This document was updated to address the following changes Added maximum rating information for VIN Input voltage see Section 8 2 on page 192 Revised VIL Maximum a...

Page 14: ...CI command code row in Table 1 on page 28 Added a new bullet in the section describing PCI commands not supported by the Tsi310 see Section 2 1 1 on page 28 Added more information about PCI to PCI tra...

Page 15: ...c Notation The following numeric conventions are used Hexadecimal values are in single quotation marks and are preceded by an x For example x 0B00 Undefined hexadecimal values are indicated by a capit...

Page 16: ...subject to change and exists until prototypes are available Preliminary The Preliminary manual contains information about a product that is near production ready and is revised as required The Prelimi...

Page 17: ...PCI X enables the design of systems and devices that can operate at speeds significantly higher than today s specification allows For more information see www pcisig com PCI to PCI Bridge Architectur...

Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...

Page 19: ...concurrent operations on both buses This results in good utilization of the buses in various system configurations and enables hierarchical expansion of I O bus structures As described by the PCI X ar...

Page 20: ...input within the architectural bounds is supported for either or both interfaces One set of configuration registers programmable either from the primary or secondary interface The first 64 bytes of t...

Page 21: ...c address decoding control logic and other control functions are also included in these blocks An arbiter for the secondary bus which can be disabled if an external arbiter is employed When enabled bu...

Page 22: ...current primary and secondary bus operations Supports configurations of PCI mode or PCI X mode on either bus in any combination 1 2 2 Memory Buffer Architecture 4KB of buffering for upstream memory bu...

Page 23: ...iguration registers accessible from both the primary and secondary interfaces Supports Type 0 and Type 1 configuration cycles 1 2 6 Optional Features Capable of defining an optional opaque undecoded m...

Page 24: ...interface Speed matching is accomplished using the buffering structure of the Tsi310 design The Tsi310 implements a 64 bit bus on both interfaces The PCI architecture also allows either side to be co...

Page 25: ...Activity generally occurs when a 128 byte segment is filled or emptied this keeps data flowing by re using 128 byte subsections as they become available 1 3 2 3 Single Data Phase Buffers There is one...

Page 26: ...vices At different points in time snapshots are taken of all pending requests for each priority level All captured HP requests are serviced first then one of the captured LP requests is serviced At th...

Page 27: ...Overview of Bus Operation on page 27 Write Transactions on page 30 Read Transactions on page 33 Configuration Transactions on page 37 2 1 Overview of Bus Operation This chapter presents a summary of t...

Page 28: ...nsactions Command Code Type of Transaction Initiates as Master Responds as Target Primary Secondary Primary Secondary 0000 Interrupt Acknowledge No No No No 0001 Special Cycle Yes Yes No No 0010 I O R...

Page 29: ...Configuration accesses on the secondary interface is limited The Tsi310 only responds to Type 1 configuration writes that get converted to special cycles going upstream as described in Section 2 4 4 o...

Page 30: ...only mode used for the memory write block command When the Tsi310 determines that a memory write transaction is to be forwarded across the bridge it first checks for empty space in the posted write b...

Page 31: ...2 1 2 PCI X to PCI Transactions When the originating bus is operating in PCI X mode and the destination bus is operating in the conventional PCI mode the Tsi310 uses the conventional memory write com...

Page 32: ...nsaction is disconnected in the middle of a continuing transfer on the originating interface the originator must present the transaction again with the updated byte count and address 2 2 2 Delayed Spl...

Page 33: ...memory read DWord In any other instance the conventional memory read command gets translated into a memory read block PCI X command The prefetching algorithm for the conventional memory read command i...

Page 34: ...less is being read the conventional transaction uses the memory read command If the PCI X transaction reads more than one DWord but does not cross a cache line boundary as indicated by the Cache Line...

Page 35: ...ta The command will either be split in the PCI X mode or delayed in the conventional PCI mode 2 3 3 Configuration Read 2 3 3 1 Type 1 Configuration Read The Type 1 configuration read command is only a...

Page 36: ...e primary and secondary data buffering control registers These registers have bits for memory read to prefetchable space memory read line and memory read multiple transactions For memory read the bits...

Page 37: ...The PCI Local Bus Specification Revision 2 2 defines two configuration transaction types Type 0 and Type 1 These two configuration formats are distinguished by the value of bus address bits 1 0 If ad...

Page 38: ...n when the following conditions are met during the address phase P_C BE 3 0 command indicates a configuration read or configuration write transaction P_AD 1 0 are b 00 P_IDSEL is asserted Bit 2 of the...

Page 39: ...e device number This number is defined by AD 15 11 of the address Type 0 configuration write transaction Each time a configuration write is initiated to the Tsi310 this device number is updated The de...

Page 40: ...ons are met during the address phase P_C BE 3 0 command indicates a configuration read or configuration write transaction P_AD 1 0 are b 01 The bus number on P_AD 23 16 is the same as the value in the...

Page 41: ...00 0000 0000 0100 x 03 00011 0000 0000 0000 1000 x 04 00100 0000 0000 0001 0000 x 05 00101 0000 0000 0010 0000 x 06 00110 0000 0000 0100 0000 x 07 00111 0000 0000 1000 0000 x 08 01000 0000 0001 0000 0...

Page 42: ...stream special cycle transactions as described in Section 2 4 4 on page 42 All upstream Type 1 configuration read transactions are ignored by the bridge The Tsi310 forwards Type 1 to Type 1 configurat...

Page 43: ...ontains the special cycle message The transaction is forwarded as a delayed transaction in PCI mode and as a split transaction in PCI X mode Once the transaction is completed on the destination bus th...

Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...

Page 45: ...ne for the secondary interface Each interface has its own clock input pin The primary interface is controlled by the P_CLK input The secondary interface and the internal arbiter are controlled by the...

Page 46: ...at least 7 68ns 7 5ns 0 180ns making the maximum frequency allowed for this case is just over 130 MHz 3 3 Mode and Clock Frequency Determination As explained in Sections 6 2 and 8 9 of the PCI X Adden...

Page 47: ...hold when a PCI X 66 client is attached The second is a strong pull up externally wired between the S_PCIXCAP and S_PCIXCAP_PU pins on the module Its value of 1k is selected to set the voltage of the...

Page 48: ...ted frequency for at least 100 s prior to the de assertion of the bus reset signal As the Tsi310 does not generate the secondary bus clock but does control the secondary bus reset signal it must detec...

Page 49: ...its own mode and frequency determination sequence The clock frequency may be adjusted based on the number of populated slots determined by the PRSNT pins of the bus Once the frequency of the S_CLK in...

Page 50: ...signals from the bridge into their benign states and sets all configuration registers within the Tsi310 to their reset values as defined in Section 2 4 on page 37 Activating the P_RST signal also caus...

Page 51: ...bit 6 of the bridge control register is set to b 1 S_RST is asserted immediately asychronously to the secondary bus clock When the secondary bus reset bit is being used to control S_RST the software...

Page 52: ...et is held on the logic in the secondary clock domain until this time period has elapsed While the internal reset is active the Tsi310 will not respond to any secondary bus transactions When the secon...

Page 53: ...The signals are driven low within a few cycles of the falling edge of S_RST they are released placed in the high Z state in the cycle following the rising edge of S_RST The Tsi310 is also required to...

Page 54: ...ate once power is reapplied and the power on sequences associated with P_RST and S_RST described in Section 3 6 1 on page 50 and Section 3 6 2 on page 51 are complete These power on sequences require...

Page 55: ...ction will not be claimed by not asserting DEVSEL and is allowed to terminate with a master abort The bridge will detect address parity errors for all transactions on both the primary and secondary in...

Page 56: ...d passed through to the secondary bus Memory accesses on the secondary bus are also compared against this register if address bits 63 20 are equal to bits 63 20 of the address defined by the combinati...

Page 57: ...such the Tsi310 will continue to prefetch data up to the amount specified by the Secondary Data Buffering Control Register offset x 42 bits 14 12 Should the initiator generate a new transaction reque...

Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...

Page 59: ...ry and secondary buses have a relationship only when those transactions cross the Tsi310 The following general ordering guidelines govern transactions crossing the Tsi310 Requests terminated with targ...

Page 60: ...he PCI modes Table 8 Tsi310 Ordering Rules PCI X Mode Bus Operation Can Row Pass Column Memory Write Split Read Request Split Write Request Split Read Completion Split Write Completion Memory Write No...

Page 61: ...ed Read Request No Yes Yes Yes Yes Delayed Write Request No Yes No Yes Yes Delayed Read Completion 1 No 2 Yesa Yes Yes Yes Yes Delayed Write Completion No Yes Yes Yes No a If the relaxed ordering bit...

Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...

Page 63: ...ration read and configuration write commands This chapter discusses the following topics Overview of Registers on page 63 Register Map on page 65 Register Summary on page 68 PCI Configuration Space He...

Page 64: ...of the PCI configuration space 1 The standard configuration is often referred to as a Type 0 PCI configuration space header because the value x 00 is stored in the PCI header type register at offset...

Page 65: ...nd x 04 Class Code Revision ID x 08 BIST Header Type Latency Timer Cache Line Size x 0C Base Address Register 0 x 10 PCI Device Header Type Region 48 bytes Base Address Register 1 x 14 Secondary Laten...

Page 66: ...Counter x 64 Reserved Discard Timer Control x 68 Reserved Retry Timer Status x 6C Reserved Opaque Memory Enable x 70 Opaque Memory Limit Opaque Memory Base x 74 Opaque Memory Base Upper 32 Bits x 78...

Page 67: ...gement Control Status x 94 Device Dependent Region Continued 192 bytes N A Reserved x 98 x AC Secondary Bus Private Device Mask x B0 Reserved x B4 Reserved Miscellaneous Control 2 x B8 Reserved x BC x...

Page 68: ...ype 80 BIST x 0F not supported 80 Base Address x 10 x 14 Optional base address register 81 Primary Bus Number x 18 Bus number of primary interface PCI segment 84 Secondary Bus Number x 19 Bus number o...

Page 69: ...a Buffering Control x 42 Provides controls for secondary bus memory operations 108 Miscellaneous Control x 44 Controls miscellaneous functions such as parity error operations 111 Arbiter Mode x 50 Con...

Page 70: ...ary requester to primary completer 140 Primary Bus Downstream Split Transaction x 8C Controls bridge buffers for forwarding Split Transactions from primary requester to secondary completer 141 Power M...

Page 71: ...the manufacturer using a unique vendor ID assigned by the PCI special interest group Address Offset x 00 Access Read only Reset Value x 1014 Vendor ID 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Acce...

Page 72: ...set x 02 Access Read only Reset Value x 01A7 Device ID 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Access Field Name and Description 15 0 RO Device ID This read only register contains the Device ID Th...

Page 73: ...sponse VGA Palette Snoop Control Memory Write and Invalidate Control Special Cycles Control Bus Master Control Memory Space Control I O Space Control 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Access...

Page 74: ...rity error is detected 5 RW VGA Palette Snoop Control 0 Disable palette snooping treat palette accesses like all other accesses 1 Enable palette snooping 4 RO Memory Write and Invalidate Control 0 Dis...

Page 75: ...able Reserved 66 MHz Capable Capabilities List Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Access Field Name and Description 15 RW Detected Parity Error Status 0 Device did not detect a parit...

Page 76: ...nsactions in PCI X mode 1 Target capable of accepting fast back to back transactions in the conventional PCI mode This bit is set by hardware when the primary interface is in PCI mode and is set to a...

Page 77: ...Value x 03 Revision ID 7 6 5 4 3 2 1 0 Bit s Access Field Name and Description 7 0 RO x 00 Revision 1 0 of the device x 01 Revision 1 1 of the device x 02 Revision 2 0 of the device Tsi310 133CE x 03...

Page 78: ...00 Restrictions Only one bit can be set at any time if multiple bits are set or if the bits are in an invalid setting these bits default to the 32 DWords setting Not supported Cache Line Size Not sup...

Page 79: ...r Masters that can burst for more than two data phases must implement this register as Read Write Address Offset x 0D Access See individual fields Reset Value x 00 in PCI mode x 40 in PCI X mode Prima...

Page 80: ...x 01 header is being used for this device 5 4 10 BIST Register This register is not supported by the Tsi310 Address Offset x 0E Access Read only Reset Value x 01 Header Type 7 6 5 4 3 2 1 0 Bit s Acc...

Page 81: ...passed through to the secondary bus Memory accesses on the secondary bus are also compared against this register if address bits 63 20 are equal to bits 63 20 of the address defined by the combinatio...

Page 82: ...for an address range of prefetchable memory operations that are passed from the primary to the secondary PCI bus 19 4 RO Reserved 3 RO Prefetchable indicator Identifies the address range defined by t...

Page 83: ...ister if address bits 63 20 are equal to bits 63 20 of the address defined by the combination of the lower memory base address register and the upper memory base address register the access is ignored...

Page 84: ...ams the value in this register The bridge uses this register to decode Type 1 configuration transactions on the secondary interface that must be converted to special cycle transactions on the primary...

Page 85: ...ation transactions on the primary interface that must be converted to Type 0 configuration transactions on the secondary interface The bridge also uses the secondary bus number register and the subord...

Page 86: ...us number register to determine when to respond to a Type 1 configuration transaction on the primary interface and pass it to the secondary interface The bridge also uses the secondary bus number regi...

Page 87: ...master Bus masters that can burst for more than two data phases must implement this register as Read Write Address Offset x 1B Access See individual fields Reset Value x 00 in PCI mode x 40 in PCI X...

Page 88: ...tions on the PCI bus Address bits 11 0 are assumed to be x 000 for the base address This register also specifies that the bridge supports 32 bit I O addressing Address Offset x 1C Access See individua...

Page 89: ...the PCI bus Address bits 11 0 are assumed to be x FFF for the limit address This register also specifies that the bridge supports 32 bit I O addressing Address Offset x 1D Access See individual field...

Page 90: ...ed Target Abort Signaled Target Abort DEVSEL Timing Master Data Parity Error Fast Back to Back Capable Reserved 66 MHz Capable Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Access Field Name an...

Page 91: ...errors encountered 1 Data parity errors encountered this bit for bus masters only 7 RO Fast Back to Back Capable 0 Target not capable of accepting fast back to back transactions in PCI X mode 1 Targe...

Page 92: ...I O transactions on the PCI Bus Address bits 19 0 are assumed to be x 0 0000 for the base address Address Offset x 20 Access See individual fields Reset Value x 8000 Non prefetchable Memory Base Addre...

Page 93: ...d I O transactions on the PCI bus Address bits 19 0 are assumed to be x F FFFF for the limit address Address Offset x 22 Access See individual fields Reset Value x 0000 Non prefetchable Memory Limit A...

Page 94: ...on the PCI bus Address bits 19 0 are assumed to be x 0 0000 for the base address This register also specifies that the bridge supports 64 bit prefetchable memory addressing Address Offset x 24 Access...

Page 95: ...s on the PCI bus Address bits 19 0 are assumed to be x F FFFF for the limit address This register also specifies that the bridge supports 64 bit prefetchable memory addressing Address Offset x 26 Acce...

Page 96: ...o specify a range of 64 bit addresses supported for prefetchable memory transactions on the PCI bus Address bits 19 0 are assumed to be x 0 0000 for the base address Address Offset x 28 Access See ind...

Page 97: ...r to specify a range of 64 bit addresses supported for prefetchable memory transactions on the PCI bus Address bits 19 0 are assumed to be x F FFFF for the limit address Address Offset x 2C Access See...

Page 98: ...its register to specify a range of 32 bit addresses supported for I O transactions on the PCI bus Address bits 11 0 are assumed to be x 000 for the base address Address Offset x 30 Access See individu...

Page 99: ...bits register to specify a range of 32 bit addresses supported for I O transactions on the PCI bus Address bits 11 0 are assumed to be x FFF for the limit address Address Offset x 32 Access See indivi...

Page 100: ...space 5 4 29 Reserved Registers These registers are reserved and return zeros when read Address Offset x 34 Access Read only Reset Value x 80 Capabilities Pointer 7 6 5 4 3 2 1 0 Bit s Access Field Na...

Page 101: ...t write x FF to this register 5 4 31 Interrupt Pin Register This register is a read only register that returns x 00 when read because the bridge does not implement any interrupt pins Address Offset x...

Page 102: ...the corresponding bit location is a 1 Reset Value x 0000 Reserved Discard Timer SERR Enable Discard Timer Status Secondary Discard Timer Primary Discard Timer Fast Back to Back Enable Secondary Bus Re...

Page 103: ...ter Abort Mode 0 Do not report master aborts return x FFFF FFFF on reads and discard data on writes 1 Report master aborts by signaling target abort if possible or by assertion of SERR if enabled If i...

Page 104: ...econdary SERR to primary SERR 0 RW Parity Error Response Enable 0 Ignore address and data parity errors on the secondary interface 1 Enable parity error detection and reporting on the secondary interf...

Page 105: ...uffering Control Register This register provides controls for memory read transactions that are initiated on the primary interface Address Offset x 40 Access See individual bit fields Reset Value x 00...

Page 106: ...de read command relaxed ordering disabled each target bus read completion transaction will be ordered with posted writes in the opposite direction traveling the same direction as the completion data F...

Page 107: ...interface is in PCI X mode 7 6 RW Primary Read Line prefetch mode bits Controls prefetching for Memory Read Line that are initiated on the primary bus 00 One cache line prefetch 01 Reserved 10 Full p...

Page 108: ...ions that are initiated on the secondary interface Address Offset x 42 Access See individual bit fields Reset Value x 0020 Reserved Maximum Memory Read Byte Count Enable Relaxed Ordering Secondary Spe...

Page 109: ...al mode read command relaxed ordering disabled each target bus read completion transaction will be ordered with posted writes in the opposite direction traveling the same direction as the completion d...

Page 110: ...W Secondary Read Line prefetch mode bits Controls prefetching for memory read line transactions that are initiated on the secondary bus 00 One cache line prefetch 01 Reserved 10 Full prefetch 11 Reser...

Page 111: ...n C6 is tied high For more information on strapping considerations see Section 6 4 on page 157 Note When designing a Tsi310 based system see the Tsi310 Device Errata document for more information abou...

Page 112: ...avior This bit defines the bridge s behavior when detecting a data parity error on a non posted write transaction 0 The bridge will pass the corrupted data sequence PERR will be asserted if enabled bu...

Page 113: ...Master Timeout Enable External Arbiter bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Access Field Name and Description 15 8 RW Arbiter Fairness Counter This is the initialization value of a counter...

Page 114: ...If the Broken Master Timeout expires the PCI Bus Grant for the device is de asserted 0 Broken Master Timeout disabled 1 Broken Master Timeout enabled The reset value is b 0 0 RO External Arbiter bit...

Page 115: ...7F Reserved Enable Arbiter 6 Enable Arbiter 5 Enable Arbiter 4 Enable Arbiter 3 Enable Arbiter 2 Enable Arbiter 1 Enable Arbiter 0 7 6 5 4 3 2 1 0 Bit s Access Field Name and Description 7 RO Reserve...

Page 116: ...iter 2 0 Disable arbitration 1 Enable arbitration 1 RW Enable Arbiter 1 0 Disable arbitration 1 Enable arbitration 0 RW Enable Arbiter 0 This bit enables arbitration for the internal bridge requests 0...

Page 117: ...e x 01 Reserved Arbiter Priority 6 Arbiter Priority 5 Arbiter Priority 4 Arbiter Priority 3 Arbiter Priority 2 Arbiter Priority 1 Arbiter Priority 0 7 6 5 4 3 2 1 0 Bit s Access Field Name and Descrip...

Page 118: ...Low priority request 1 High priority request 1 RW Arbiter Priority 1 0 Low priority request 1 High priority request 0 RW Arbiter Priority 0 This bit indicates the priority for the internal bridge requ...

Page 119: ...detected on the destination bus on an error free posted write 0 Assert SERR and set bit 14 of the status register if the SERR enable bit 8 in the command register is set Discard the delayed transactio...

Page 120: ...r has expired 0 Assert SERR and update status bit 14 in the status register if the primary retry counter expires and SERR enable bit 8 in the command register is set Discard the transaction and set bi...

Page 121: ...n x 0000 0100 256 retries before expiration x 0001 0000 64K retries before expiration x 0100 0000 16M retries before expiration x 8000 0000 2G retries before expiration Address Offset x 60 Access Read...

Page 122: ...5 Configuration Registers 122 Tsi310 User Manual 80B6020_MA001_05 15 9 RO Reserved 8 RW This bit used to indicate 256 retries before expiration 7 0 RO Reserved Bit s Access Field Name and Description...

Page 123: ...on x 0000 0100 256 retries before expiration x 0001 0000 64K retries before expiration x 0100 0000 16M retries before expiration x 8000 0000 2G retries before expiration Address Offset x 64 Access Rea...

Page 124: ...5 Configuration Registers 124 Tsi310 User Manual 80B6020_MA001_05 15 9 RO Reserved 8 RW This bit used to indicate 256 retries before expiration 7 0 RO Reserved Bit s Access Field Name and Description...

Page 125: ...ransaction is discarded data buffers and control resources are freed and the appropriate status bit is set in the retry and timer status register Address Offset x 68 Access Read Write Reset Value x 00...

Page 126: ...1 Use 26 PCI clocks for the value of the secondary discard timer 1 RW Primary Discard Timer Disable Controls the disabling of the primary discard timer in conjunction with bit 11 of the bridge contro...

Page 127: ...Retry Counter Status Secondary Retry Counter Status 7 6 5 4 3 2 1 0 Bit s Access Field Name and Description 7 4 RO Reserved 3 RW Primary Discard Timer Status 0 The primary discard timer has not expire...

Page 128: ...primary or secondary interfaces Address Offset x 70 Access Read Write Reset Value x 00 When OPAQUE_EN pin AA18 is tied low For more information on strapping considerations see Section 6 4 on page 157...

Page 129: ...ondary buses This address range is enabled by bit 0 of the opaque memory enable register Bits 19 0 of the base address are assumed to be x 0 0000 This register also specifies that the bridge supports...

Page 130: ...secondary buses This address range is enabled by bit 0 of the opaque memory enable register Bits 19 0 of the limit address are assumed to be x F FFFF This register also specifies that the bridge supp...

Page 131: ...ndary bus These memory addresses will not be accepted by the bridge on the primary or the secondary buses This address range is enabled by bit 0 of the opaque memory enable register Address Offset x 7...

Page 132: ...y bus These memory addresses will not be accepted by the bridge on the primary or the secondary buses This address range is enabled by bit 0 of the Opaque Memory Enable register Address Offset x 7C Ac...

Page 133: ...pabilities list as a PCI X register set It is read only returning x 07 when read Address Offset x 80 Access Read only Reset Value x 07 PCI X Capability ID 7 6 5 4 3 2 1 0 Bit s Access Field Name and D...

Page 134: ...y register returning x 90 when read indicating that there are more list items in the capabilities list Address Offset x 81 Access Read only Reset Value x 90 Next Capabilities Pointer 7 6 5 4 3 2 1 0 B...

Page 135: ...ected Split Completion Split Completion Discarded 133 MHz Capable 64 bit Device 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Access Field Name and Description 15 9 RO Reserved 8 6 RO Secondary Clock Fr...

Page 136: ...he bridge has accepted all split completions 1 The bridge has terminated a split completion with retry or disconnect at next ADB because the bridge buffers were full 3 RW Unexpected Split Completion T...

Page 137: ...and Description 31 22 RO Reserved 21 RW Split Request Delayed This bit is set any time the bridge has a request to forward a transaction to the primary bus but cannot because there is not enough room...

Page 138: ...een discarded 17 RO 133 MHz Capable This bit is read only and is a b 1 indicating that this bridge is capable of 133 MHz operation on the primary interface 16 RO 64 bit Device This bit is read only an...

Page 139: ...te regardless of which register in the bridge is addressed by the transaction The bridge is addressed by a configuration write transaction if all of the following are true The transaction uses a confi...

Page 140: ...less than the contents of the split transaction capacity field causes unspecified results The Tsi310 will forward split requests as shown below according to the value programmed in the Split transact...

Page 141: ...s than the contents of the split transaction capacity field causes unspecified results The Tsi310 will forward split requests as shown below according to the value programmed in the Split transaction...

Page 142: ...t there are no more list items in the capabilities list Address Offset x 90 Access Read only Reset Value x 01 Power Management ID 7 6 5 4 3 2 1 0 Bit s Access Field Name and Description 7 0 RO Power M...

Page 143: ...icate that this device does not support the D2 power management state 9 RO D1 Support Forced to b 0 to indicate that this device does not support the D1 power management state 8 6 RO Aux Current Force...

Page 144: ...cate that this device does not implement the Data register 12 9 RO Data Select Forced to b 0000 to indicate that this device does not implement the Data register 8 RO PME Enable Forced to b 0 to indic...

Page 145: ...ead only Reset Value x 00 Bus Power Clock Control Enable B2 B3 Support for D3 hot Reserved 7 6 5 4 3 2 1 0 Bit s Access Field Name and Description 7 RO Bus Power Clock Control Enable Forced to b 0 to...

Page 146: ...eset Value x 22F2 0000 When IDSEL_REROUTE_EN pin AC22 is tied high For more information on strapping considerations see Section 6 4 on page 157 Reserved Private Device Mask 13 Reserved Private Device...

Page 147: ...configuration transactions to device 6 assert S_AD pin 31 instead 21 RW Private Device Mask 5 0 Rerouting disabled for device 5 1 Block assertion of S_AD pin 21 for configuration transactions to devi...

Page 148: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Access Field Name and Description 15 R W Short Term Caching This bit controls the Short Term Caching feature of the Tsi310 0 Disabled 1 Enabled Note A clear under...

Page 149: ...s been prefetched or the initiator disconnects 8 RW Secondary Prefetch Persistence Control Affects the how the bridge reacts to target disconnect when prefetching data on the primary bus for read tran...

Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...

Page 151: ...ignals Table 13 Primary Interface Signals Signal Name I O Width Description P_ACK64 I O 1 Acknowledge 64 Bit Transfer Asserted by the currently addressed target on the primary bus to indicate its will...

Page 152: ...p select during configuration read and write transactions on the primary bus P_IRDY I O 1 Initiator Ready Indicates the ability of the initiator on the primary bus to complete the current data phase o...

Page 153: ...al reports address parity errors and other system errors where the results will be catastrophic P_SERR is driven by the bridge when detecting such errors on the primary bus or in the case of an error...

Page 154: ...dress of the current transaction as being within one of its address ranges S_DEVSEL is monitored by the bridge when performing a secondary bus transaction on behalf of a primary bus master S_DEVSEL is...

Page 155: ...bit for the upper half of the address data and command byte enable buses on the secondary interface It provides even parity across S_AD 63 32 and S_C BE 7 4 S_PERR I O 1 Parity Error Used to report da...

Page 156: ...ting that the initiator stop the current transaction on the secondary bus S_STOP is monitored by the bridge when performing a secondary bus transaction on behalf of a primary pus master S_STOP is driv...

Page 157: ...cesses and the associated memory region is not claimed when disabled 0 BAR disabled register reads returns 0 s no memory region claimed 1 BAR enabled bits 63 20 can be written by software to claim a 1...

Page 158: ...rol Used to alter the output impedance of the primary bus PCI PCI X drivers to account for how many drops are on the bus This line should be pulled through a resistor to a high or a low as needed Inte...

Page 159: ...ossible states of the S_PCIXCAP input signal A 1k resistor must be placed on the board and wired between this signal and S_PCIXCAP S_SEL100 I 1 Secondary Bus 100 MHz Indicator Used to choose between 1...

Page 160: ...T I 1 JTAG Test Reset Provides an asynchronous initialization of the TAP controller within the bridge Internal pull up T_DI1 I 1 Driver Inhibit 1 Used to tri state the outputs of non test drivers duri...

Page 161: ...h wide tracks that are as short as possible The necessary characteristics for inductor L1 can be found in Table 18 and Figure 6 Figure 5 Filter Requirements for P_VDDA and S_VDDA Table 17 Power and Gr...

Page 162: ...nual 80B6020_MA001_05 Figure 6 Inductor L1 Impedance Table 18 Inductor L1 Characteristics Parameter Value Impedance 100 MHz 20 C 70 Ohms Rated current 200 mA DC resistance 0 15 Ohms 100 75 50 25 0 1 1...

Page 163: ...sts the pinout in numerical order according to signal name Table 20 on page 167 lists the pinout in alphabetical order according to grid position Figure 7 Pinout Viewed from Above Looking Through the...

Page 164: ...3 B1 GND A18 GND AC1 P_AD 42 F2 GND A23 GND AC6 P_AD 41 G3 GND B2 GND AC10 P_AD 40 H3 GND B22 GND AC13 P_AD 39 H2 GND C3 GND AC14 P_AD 38 E1 GND C21 GND AC18 P_AD 37 J3 GND D4 GND AC23 P_AD 36 G1 GND...

Page 165: ...D 54 V4 S_AD 17 V22 P_C BE 6 B12 S_AD 53 U2 S_AD 16 V21 P_C BE 5 C11 S_AD 52 U3 S_AD 15 W21 P_C BE 4 A5 S_AD 51 T2 S_AD 14 V20 P_C BE 3 A15 S_AD 50 T3 S_AD 13 AA20 P_C BE 2 D14 S_AD 49 R2 S_AD 12 AB18...

Page 166: ...S_GNT3 Y2 T_RI W22 VDD2 G4 S_GNT4 AC5 P_VDDA A21 VDD2 G20 S_GNT5 AB4 S_VDDA AB21 VDD2 H23 S_GNT6 AC4 VDD D9 VDD2 M1 S_IDSEL AA22 VDD D11 VDD2 T1 S_INT_ARB_EN T21 VDD D13 VDD2 U4 S_IRDY AC19 VDD D15 V...

Page 167: ...64 A9 T_MODECTL C1 GND D16 GND A10 P_AD 48 C2 VDD2 D17 GND A11 GND C3 P_AD 11 D18 VDD2 A12 P_STOP C4 VDD2 D19 P_C BE 0 A13 VDD2 C5 GND D20 GND A14 P_CFG_BUSY C6 P_DEVSEL D21 P_C BE 3 A15 P_AD 53 C7 JT...

Page 168: ...D 44 W1 VDD J4 S_AD 45 P3 S_REQ3 W2 VDD J20 S_AD 43 P4 S_CLK_STABLE W3 P_AD 20 J21 S_AD 26 P20 VDD2 W4 P_AD 19 J22 S_AD 28 P21 VDD2 W20 P_AD 31 J23 S_AD 29 P22 S_AD 15 W21 GND K1 GND P23 T_RI W22 S_AD...

Page 169: ...02 AC9 S_AD 59 AA6 S_AD 63 AB8 GND AC10 S_AD 61 AA7 S_AD 01 AB9 S_AD 03 AC11 S_ACK64 AA8 S_C BE 6 AB10 VDD2 AC12 S_AD 00 AA9 S_AD 04 AB11 GND AC13 S_PAR64 AA10 S_C BE 0 AB12 GND AC14 S_C BE 5 AA11 S_R...

Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...

Page 171: ...Scan Architecture to facilitate card and board testing using boundary scan techniques This function consists of the following major components The five signal test port interface with the signals JTG...

Page 172: ...in a JTAG scan ring use an independent buffer on the inputs to TCK and TRST The Tsi310 contains internal pull ups on the following JTAG signals TMS TDI TCK and TRST According to sections 4 3 3 and 4...

Page 173: ...he JTG_TDI input and the JTG_TDO output This abbreviated scan path is selected by the BYPASS instruction code and is used to shorten the overall scan ring length during board level testing when the Ts...

Page 174: ...ing Several varieties of boundary scan cells are possible selected according to the function of the signal pin with which they are associated Input only pins For device inputs that are not shared with...

Page 175: ...and IBM1149_BSR_FASTENAB While they perform the same boundary scan function they differ in that the IBM1149_BSR_FASTENAB cell has a faster functional path through it It is often used on timing critic...

Page 176: ...P_AD 20 BIDIR 229 22 IBM1149_BSR_BIDI P_AD 21 BIDIR 230 23 IBM1149_BSR_BIDI P_AD 22 BIDIR 231 24 IBM1149_BSR_BIDI P_AD 23 BIDIR 232 25 IBM1149_BSR_BIDI P_AD 24 BIDIR 233 26 IBM1149_BSR_BIDI P_AD 25 BI...

Page 177: ...47 BIDIR 256 49 IBM1149_BSR_BIDI P_AD 48 BIDIR 257 50 IBM1149_BSR_BIDI P_AD 49 BIDIR 258 51 IBM1149_BSR_BIDI P_AD 50 BIDIR 259 52 IBM1149_BSR_BIDI P_AD 51 BIDIR 260 53 IBM1149_BSR_BIDI P_AD 52 BIDIR 2...

Page 178: ...SR_BIDI P_FRAME BIDIR 282 76 IBM1149_BSR_IN P_GNT INPUT 77 IBM1149_BSR_IN_SIO P_IDSEL INPUT 78 IBM1149_BSR_BIDI P_IRDY BIDIR 283 79 IBM1149_BSR_BIDIIN P_LOCK INPUT 80 IBM1149_BSR_IN_SIO P_DRVR_MODE IN...

Page 179: ...R 303 103 IBM1149_BSR_BIDI S_AD 11 BIDIR 304 104 IBM1149_BSR_BIDI S_AD 12 BIDIR 305 105 IBM1149_BSR_BIDI S_AD 13 BIDIR 306 106 IBM1149_BSR_BIDI S_AD 14 BIDIR 307 107 IBM1149_BSR_BIDI S_AD 15 BIDIR 308...

Page 180: ...D 37 BIDIR 330 130 IBM1149_BSR_BIDI S_AD 38 BIDIR 331 131 IBM1149_BSR_BIDI S_AD 39 BIDIR 332 132 IBM1149_BSR_BIDI S_AD 40 BIDIR 333 133 IBM1149_BSR_BIDI S_AD 41 BIDIR 334 134 IBM1149_BSR_BIDI S_AD 42...

Page 181: ...S_CBE 0 BIDIR 357 157 IBM1149_BSR_BIDI S_CBE 1 BIDIR 358 158 IBM1149_BSR_BIDI S_CBE 2 BIDIR 359 159 IBM1149_BSR_BIDI S_CBE 3 BIDIR 360 160 IBM1149_BSR_BIDI S_CBE 4 BIDIR 361 161 IBM1149_BSR_BIDI S_CBE...

Page 182: ...DIR 371 183 IBM1149_BSR_IN S_REQ1GNT INPUT 184 IBM1149_BSR_IN S_REQ2 INPUT 185 IBM1149_BSR_IN S_REQ3 INPUT 186 IBM1149_BSR_IN S_REQ4 INPUT 187 IBM1149_BSR_IN S_REQ5 INPUT 188 IBM1149_BSR_BIDI S_REQ64...

Page 183: ...FASTENAB CONTROL 210 IBM1149_BSR_FASTENAB CONTROL 211 IBM1149_BSR_FASTENAB CONTROL 212 IBM1149_BSR_FASTENAB CONTROL 213 IBM1149_BSR_FASTENAB CONTROL 214 IBM1149_BSR_FASTENAB CONTROL 215 IBM1149_BSR_FA...

Page 184: ...49_BSR_FASTENAB CONTROL 237 IBM1149_BSR_FASTENAB CONTROL 238 IBM1149_BSR_FASTENAB CONTROL 239 IBM1149_BSR_FASTENAB CONTROL 240 IBM1149_BSR_FASTENAB CONTROL 241 IBM1149_BSR_FASTENAB CONTROL 242 IBM1149...

Page 185: ...49_BSR_FASTENAB CONTROL 264 IBM1149_BSR_FASTENAB CONTROL 265 IBM1149_BSR_FASTENAB CONTROL 266 IBM1149_BSR_FASTENAB CONTROL 267 IBM1149_BSR_FASTENAB CONTROL 268 IBM1149_BSR_FASTENAB CONTROL 269 IBM1149...

Page 186: ...49_BSR_FASTENAB CONTROL 291 IBM1149_BSR_FASTENAB CONTROL 292 IBM1149_BSR_FASTENAB CONTROL 293 IBM1149_BSR_FASTENAB CONTROL 294 IBM1149_BSR_FASTENAB CONTROL 295 IBM1149_BSR_FASTENAB CONTROL 296 IBM1149...

Page 187: ...49_BSR_FASTENAB CONTROL 318 IBM1149_BSR_FASTENAB CONTROL 319 IBM1149_BSR_FASTENAB CONTROL 320 IBM1149_BSR_FASTENAB CONTROL 321 IBM1149_BSR_FASTENAB CONTROL 322 IBM1149_BSR_FASTENAB CONTROL 323 IBM1149...

Page 188: ...49_BSR_FASTENAB CONTROL 345 IBM1149_BSR_FASTENAB CONTROL 346 IBM1149_BSR_FASTENAB CONTROL 347 IBM1149_BSR_FASTENAB CONTROL 348 IBM1149_BSR_FASTENAB CONTROL 349 IBM1149_BSR_FASTENAB CONTROL 350 IBM1149...

Page 189: ...BM1149_BSR_FASTENAB CONTROL 367 IBM1149_BSR_FASTENAB CONTROL 368 IBM1149_BSR_FASTENAB CONTROL 369 IBM1149_BSR_FASTENAB CONTROL 370 IBM1149_BSR_FASTENAB CONTROL 371 IBM1149_BSR_FASTENAB CONTROL 372 IBM...

Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...

Page 191: ...s on page 193 AC Operating Conditions on page 193 Power Dissipation on page 194 8 1 PCI PCI X Specification Conformance Most of the Tsi310 interface signals are delineated by the PCI and PCI X specifi...

Page 192: ...indicated in this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect the reliability of the Tsi310 Table 23 Absolute Maximum Ratings Symbol Par...

Page 193: ...D2 VDD2 0 5 V 1 VIL Input Low Voltage 0 5 0 35VDD2 V 1 CIN Input Pin Capacitance 8 0 pF 1 All voltages referenced to GND Table 25 AC Operating Conditions TA 0 to 70 C Symbol Parameter Rating Units Not...

Page 194: ...2 4 2 8 2 1 0 7 3 3 133 66 12 36 2 3 2 7 2 1 0 6 3 2 133 66 12 24 2 2 2 6 2 1 0 5 3 0 133 66 12 12 2 1 2 5 2 1 0 4 2 9 100 66 24 48 2 5 3 0 2 1 0 9 3 5 100 66 24 36 2 4 2 9 2 1 0 8 3 4 100 66 24 24 2...

Page 195: ...y or Secondary Interface power dissipation however is not affected by the type of connection b For PCI 33 MHz applications use the 66 MHz numbers c All power estimates use a 12pF value as equivalent t...

Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...

Page 197: ...Characteristics on page 197 Thermal Characteristics on page 199 9 1 Package Characteristics Tsi310 s package characteristics are summarized in the following table Figure 8 displays Tsi310 s package di...

Page 198: ...W V U T R P N M L K J H G F E D C B A C PCB Stiffener 304X 0 75 0 15 Solder Ball Bottom of Package HPBGA Side Up Encapsulation Note All measurements are in millimeters Substrate 23 22 21 20 19 18 17...

Page 199: ...i310 Junction temperature C 125 C ja Ambient to Junction Thermal Impedance C Watt see Table 28 P Tsi310 power consumption Watts see Table 25 on page 193 The ambient to junction thermal impedance ja is...

Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...

Page 201: ...mation IDT Tsi products are designated by a product code When ordering please refer to the Tsi310 by its full part number as displayed in the following table Table 29 Ordering Information Part Number...

Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...

Page 203: ...ck input pin 45 clock jitter 46 clock stability 48 clocking domains 45 Command Register 73 configuration cycles type 0 23 type 1 23 configuration transactions 37 special cycle generation 42 type 0 38...

Page 204: ...3 P_STOP signal 153 P_TRDY signal 153 P_VDDA signal 161 package characteristics 197 package diagram 198 packaging information 197 parity error 55 parity errors 55 PCI buffers 24 PCI transactions 28 PC...

Page 205: ...ry Bus Number Register 85 Secondary Bus Private Device Mask Register 146 Secondary Bus Upstream Split Transaction Register 140 Secondary Data Buffering Control Register 108 Secondary Latency Timer Reg...

Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...

Page 207: ...products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any p...

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