2. Bus Operation
42
Tsi310 User Manual
80B6020_MA001_05
2.4.3
Type 1 to Type 1 Forwarding by Bridge
Type 1 to Type 1 transaction forwarding provides a means to configure devices when a
hierarchical bus structure containing two or more levels of bridges is used.
When the Tsi310 accepts a Type 1 configuration transaction destined for a PCI/PCI-X bus
downstream from its secondary interface, the bridge forwards the transaction unchanged to the
secondary bus. Eventually, this transaction is translated to a Type 0 configuration transaction or
to a special cycle transaction by a downstream bridge.
Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during
the address phase:
•
P_C/BE(3:0)# command indicates a configuration read or configuration write transaction
•
P_AD(1:0) are equal to b‘01’
•
the specified bus number is within the range defined by the secondary bus number register
(exclusive) and the subordinate bus number register (inclusive)
The Tsi310 also supports Type 1 to Type 1 forwarding of configuration write transactions
upstream to allow for the generation of upstream special cycle transactions, as described in
. All upstream Type 1 configuration read transactions are ignored by
the bridge.
The Tsi310 forwards Type 1 to Type 1 configuration read and configuration write transactions
as delayed transactions in PCI mode, and as split transactions in PCI-X mode.
2.4.4
Special Cycle Generation by the Bridge
The Type 1 configuration transaction format may be used to generate special cycle transactions
in hierarchical PCI/PCI-X systems. Special cycle transactions can be generated from Type 1
configuration write transactions in either the upstream or the downstream direction.
The Tsi310 initiates a special cycle on the destination bus when a Type 1 configuration write
transaction is detected on the initiating bus and the following conditions are met during the
address phase:
•
The command is a configuration write
•
Address bits AD(1:0) are b‘01’
•
The device number in address bits AD(15:11) is equal to b‘11111’
•
The function number in address bits AD(10:8) is equal to b‘111’
•
The register number in address bits AD(7:2) is equal to b‘000000’
•
The specified bus number is the same as the value in Tsi310’s secondary bus number
register (for downstream transactions) or matches the value in its primary bus number
register (for upstream transactions)
Summary of Contents for Tsi310TM
Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...
Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...
Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...
Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...
Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...
Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...
Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...
Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...
Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...
Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...
Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...
Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...
Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...
Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...