IDT Tsi310TM, User Manual

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Tsi310 User Manual
80B6020_MA001_05
7. JTAG Boundary Scan
This chapter discusses the following topics:
• “Overview of JTAG Boundary Scan” on page 171
• “TAP Controller Initialization” on page 172
• “JTAG Design Considerations” on page 172
• “Instruction Register and Codes” on page 173
• “Bypass Register” on page 173
• “JTAG Device ID Register” on page 174
• “Boundary Scan Register” on page 174
7.1 Overview of JTAG Boundary Scan
The Tsi310 provides a JTAG test port that is compliant with IEEE Standard 1149.1, IEEE
Standard Test Access Port and Boundary Scan Architecture, to facilitate card and board testing
using boundary scan techniques. This function consists of the following major components:
• The five signal test port interface with the signals JTG_TCK, JTG_TDI, JTG_TDO,
JTG_TMS, and JTG_TRST# (see
Section 6 on page 151 for additional information on
these signals)
• The test access port (TAP) controller
• The instruction register (IR) and its associated instruction decoder
• The bypass register
• The device ID register
• The boundary scan register
The JTAG test port is intended to be used only while the Tsi310 is not operating in a functional
mode. The information presented in this section is available in a standardized, soft-copy format
called a boundary scan description language (BSDL) file.