IDT PhiClock 9FGV1001, User Manual

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8 ©2018 Integrated Device Technology, Inc. March 1, 2018
9FGV1001, 9FGV1002, and 9FGV1004 PhiClock™ PCIe Evaluation Board User Guide
Figure 7. 9FGV100x Evaluation Board Schematic – page 3
5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
Loc
ate near
D
U
T
pow
er
pi
n
LA
BEL
O
N
E
ACH
RE
S
P
ECT
I
V
E
PI
N
O
F
HE
ADE
R
S
:
1
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V
, 2
.
5
V
, 3.3
V
He
ader
Al
ignm
ent
:
S
i
ngle
pi
n h
ead
er
abov
e
an
d b
elo
w th
e c
ent
er
pin
of
3-p
in head
er so that
ce
nter
pi
n ca
n b
e
j
umpe
d
wi
th t
he
surr
oun
din
g
4
pi
ns,
sho
wn a
s
l
eft
Loc
ate near
D
U
T
pow
er
pi
n
VDDO
_
J
GN
D
GN
D
GN
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VDD_
J
VDDAp
VDDDp
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D
GN
D
GN
D
GN
D
VDDREF
p
VDDO
0
VDDO
1
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
VDDO
3
GN
D
GN
D
VDDO
2
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
USB_5
V
{3
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}
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tl
e
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e
Do
c
u
m
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n
t Nu
m
b
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r
Re
v
D
a
te
:
S
h
eet
of
1
9F
G
S
90
91
E
V
B
R
E
V
B
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34
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e
s
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16
,
20
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e
Do
c
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m
e
n
t Nu
m
b
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r
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v
D
a
te
:
S
h
eet
of
1
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S
90
91
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34
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e
s
d
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gust
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,
20
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e
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c
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te
:
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eet
of
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90
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34
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e
s
d
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u
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16
,
20
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60
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m
500
m
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2
1
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_
2
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0
0
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uF
1 2
R6
6
POT_ 25 K_ NP
1 3
2
FB
1
6
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m
50
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A
2
1
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o
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r Jack R
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d
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7
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1
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F
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60
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m
500
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A
2
1
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6
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1
u
F
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8
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1u
F
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r Jack B
lack
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4
POT _2 5K_ NP
1 3
2
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7
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P
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6
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m
50
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A
2
1
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6
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F
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4
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1
u
F
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1u
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1 2
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6
6
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m
50
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A
2
1
1 2
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5
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P
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3
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7
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4
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0
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1u
F
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C1
5
1
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387
89
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1
IN
2
IN
(CP
)
3
CP
4
EN
5
GN
D(C
P
)
6
GN
D
7
FB
8
SE
T
9
OU
T
(F
B
)
10
OU
T
11
OU
T
12
EPAD
13
EPAD
14
EPAD
15
EPAD
16
EPAD
17
EPAD
18
EPAD
19
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20
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21
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2
10
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FB
5
6
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m
50
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K
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1
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9
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1
u
F
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3 2 5
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3 2 5
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F
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C1
6
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1u
F
1 2
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P
38
789
IN
1
IN
2
IN
(CP
)
3
CP
4
EN
5
GN
D(C
P
)
6
GN
D
7
FB
8
SE
T
9
OU
T
(F
B
)
10
OU
T
11
OU
T
12
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13
EPAD
14
EPAD
15
EPAD
16
EPAD
17
EPAD
18
EPAD
19
EPAD
20
EPAD
21
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8
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9
23
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K
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1
%
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9
1
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7
6
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50
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A
2
1
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P
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r Jack R
e
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1
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4
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1u
F
1 2
U5 L
P
38
789
IN
1
IN
2
IN
(CP
)
3
CP
4
EN
5
GN
D(C
P
)
6
GN
D
7
FB
8
SE
T
9
OU
T
(F
B
)
10
OU
T
11
OU
T
12
EPAD
13
EPAD
14
EPAD
15
EPAD
16
EPAD
17
EPAD
18
EPAD
19
EPAD
20
EPAD
21
C3
8
1
0uF
R3
6
2
1
K
_
1
%
1
2
R
4
0
1
3.
3K
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1
%
1
2
R3
7
16
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K
_
1
%
1 2
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3 2 5
4 1
C3
5
10
uF
VDDO
_
J
VDDO
_
J
VDDO
_
J
G
ND_
J
VDD_
J
R3
1
_
C3
1
USB_5
V
VDDO
_
1
.8
V
VDDO
_
1
VDD_
REFp
VDDO
_
0
USB_5
V
R32 _C4 5
USB_5
V
R33 _C4 8
USB_5
V
VDDO
_
3
.3
V
R36 _C5 6
GN
D
VDDO
_
2
.5
V
VDDO
_
3
.3
V
VDDO
_
1
.8
V
VDDO
_
2
.5
V
VDDO
_
3
.3
V
VDDO
_
1
.8
V
VDDO
_
2
.5
V
VDDO
_
3
.3
V
VDDO
_
1
.8
V
VDDO
_
2
.5
V
VDDO
_
3
.3
V
VDDO
_
1
.8
V
VDDO
_
3
VDDO
_
2
.5
V
VDDO
_
2
.5
V
VDDO
_
3
.3
V
VDDO
_
1
.8
V
VDDO
_
2
VDDO
_
J
VDDO
_
J
VDDO
_
2
.5
V
VDDO
_
3
.3
V
VDDO
_
1
.8
V
VDDA_
V
D
D
D
VDDA_
p
REG
_
C
P
3
REG
_
SET
3
REG
_
D
3
REG
_
C
P
4
REG
_
SET
4
REG
_
D
4
REG
_
C
P
5
REG
_
SET
5
REG
_
D
5