IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 95 / 744

IDT Switch Core
PES32NT24xG2 User Manual 4 - 17 January 30, 2013
Notes
Each internal error status bit has an associated severity bit in the Internal Error Severity (IERRORSEV0/
1) registers. When an unmasked internal error is detected, the error is reported as dictated by the corre-
sponding severity bit (i.e., either an uncorrectable internal error or a correctable internal error). When an
uncorrectable or correctable internal error is reported, the corresponding AER status bit is set and
processed as dictated by the PCI Express Base Specification.
If the internal error severity in the IERRORSEV0/1 register is set to uncorrectable, then the UIE bit is set
in the AERUES register. Once this bit is set, the error is reported to the root-complex as specified in the PCI
Express Base Specification. Note that while the UIE bit is set, the detection of a subsequent uncorrectable
internal error is ignored by the AER mechanism and not reported to the root-complex. Still, the appropriate
bit is logged in the IERRORSTS0/1 registers regardless of the setting of the UIE bit.
If the internal error severity in the IERRORSEV0/1 register is set to correctable, then the CIE bit is set in
the AERCES register. Once this bit is set, the error is reported to the root-complex as specified in the PCI
Express Base Specification. Note that while the CIE bit is set, the detection of a subsequent correctable
internal error is ignored by the AER mechanism and not reported to the root-complex. Still, the appropriate
bit is logged in the IERRORSTS0/1 registers regardless of the setting of the CIE bit.
Figure 4.7 shows a logical representation of the internal error circuitry within each PES32NT24xG2 port.
Figure 4.7 Internal Error Logic in Each PES32NT24xG2 Port
To facilitate testing of software error handlers, the occurrence of an internal error may be emulated by
writing a value of one to the corresponding bit position in the Internal Error Test (IERRORTST0/1) registers.
Once a bit is set in IERRORSTS0/1 registers, it is processed as though the actual error occurred (e.g.,
logged in the IERRORSTS0/1 register, reported by AER, etc.)
Error emulation via the IERRORTST0/1 registers is only applicable to the PCI-to-PCI bridge function.
The logging of internal errors in the AER capability structure of the NT and DMA functions is not possible
via the IERRORSTS0/1 registers.
1
Switch Core Time-Outs
The switch core discards any TLP that reaches the head of an IFB or EFB queue and is more than 64
seconds old. This includes posted, non-posted, completion and inserted TLPs. Whenever a TLP is
discarded by a port due to a switch time-out, a bit corresponding to the type of TLP that was discarded is
1.
It is possible to test logging of internal errors in the NT functions by using the AER Emultion Registers in this
function. Refer to section Error Emulation Control in the NT Function on page 14-39 for details.
IERRORSTS0/1
IERRORSEV0/1
IERRORCTL.IERROREN
P2PIERRORMSK0/1
UIE
CIE
AERUES AERCES
PCI-to-PCI Bridge Function
NTIERRORMSK0/1
UIE
CIE
AERUES AERCES
NT Function
DMAIERRORMSK0/1
UIE
CIE
AERUES AERCES
DMA Function
Port
Internal Error
Detection Logic