IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 726 / 744

IDT Usage Models
PES32NT24xG2 User Manual 26 - 16 January 30, 2013
Notes
Figure 26.9 System Configuration after Serial EEPROM Initialization
Description
The serial EEPROM configures switch #1 as shown in Figure 26.9.
– Partitions 0 and 1 are placed in active state.
– Ports 4 and 6 are configured as downstream switch ports in partition 0.
– Port 8 is configured in NT function mode in partition 1.
– Port 0 is configured as an upstream switch port with NT endpoint in partition 0.
– This configuration is achieved by writing to Switch Partition Control (SWPARTxCTL) and Switch
Port Control (SWPORTxCTL) registers in switch #1.
Note that the sequence shown above modifies the state of partitions 0 and 1 to active before adding
ports to the partitions. This ensures that the links of these ports are not reset or disabled when the ports are
migrated into the partition.
The serial EEPROM is also in charge of configuring switch #2. To do so, the serial EEPROM instruction
sequence performs the following steps.
– The NT function in port 8 of switch #1 is directed to issue punch-through configuration requests.
These configuration requests are sent from port 8 in switch #1 to port 8 in switch #2, via the cross-
link formed between these devices.
– The punch-through configuration requests target function 0 of the port 8 in switch #2. Specifically,
the punch-through configuration requests target the global space access registers (i.e.,
GASAADDR and GASADATA). Through these registers, any other register in the switch #2 may
be accessed (e.g., the switch partition and control registers), thereby making it possible to
configure partitions in the switch #2.
For example, to issue a punch-through type 0 configuration write request targeting the GASAADDR
register in function 0 of port 8 in switch #2, the serial EEPROM instruction sequence performs the following
actions:
– Write the following values to the Punch Through Configuration Control 0 (PTCTL0) register of the
NT function in port 8 of switch #1. The PTCTL0 register is located at address 0x11510 in the
switch’s global address space
1
:
1.
This address is derived by summing the global address space base address of the NT function in port 8 (i.e.,
0x11000) to the offset of the PTCTL0 register within the NT function’s configuration space (i.e., 0x510).
RC1
EP EP
Partition 0
P2P
P4
(P2P)
P6
(P2P)
Switch #1
NT
P8
(NT)
Part 1
RC2
EP EP
Partition 0
P2P
P6
(P2P)
P4
(P2P)
Switch # 2
NT
P8
(NT)
Part 1
NT Crosslink
Serial
EEPROM
Port 0
Port 0