IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 712 / 744

IDT Usage Models
PES32NT24xG2 User Manual 26 - 2 January 30, 2013
Notes
Stack 3 will operate with one x8 port. To achieve this configuration, the STK3CFG[4:0] pins of the device
can be tied to the appropriate value (refer to Table 3.7) on the system board. Alternatively, regardless of the
value of the STK3CFG[4:0] pins, the stack may be dynamically reconfigured via serial EEPROM as follows:
1. For all ports associated with stack 3 (i.e., ports 16 to 23), the operating mode of each port is modified
to ‘Disabled’ (i.e., via the SWPORTxCTL register).
– Follow the guidelines in section Port Operating Mode Change via EEPROM on page 5-15.
– The EEPROM Wait configuration block should be used to determine when the port operating
mode change has completed, prior to executing the next step. Refer to section Initialization from
Serial EEPROM on page 12-3.
2. Stack 3 is reconfigured to operate with one x8 port, by programming the STK3CFG register to the
appropriate value (refer to Table 3.7). Note that only port 16 will be active in this configuration. Other
ports in this stack (i.e., ports 17 to 23) are de-activated, regardless of the operating mode of those
ports.
3. The operating mode of port 16 is modified to upstream switch port mode (i.e., via the
SWPORT16CTL register).
4. The operating mode of ports 0 to 15 is modified to downstream switch port mode.
– While the serial EEPROM loading executes, the switch is kept in quasi-reset mode (see section
Partition Resets on page 3-11). To meet PCI Express conventional reset requirements, serial
EEPROM configuration completes within 1 second after the de-assertion of fundamental reset.
– After EEPROM loading completes, the switch exits quasi-reset mode and the root complex can
proceed to enumerate and configure the device. The root complex will find a switch with one x8
upstream port (port 16) and sixteen x1 downstream ports (ports 0 to 15). No other ports logically
visible to enumeration software.
Port Clocking Configuration
Goal
Configure the switch (via serial EEPROM) such that the upstream port operates in local port clocked
mode, and the downstream ports operate in global clocked mode.
Assumptions
– PES24NT6AG2 switch device.
– The switch boots in switch mode “Single partition with Serial EEPROM initialization”.
– Upstream port: Port 0 (x8)
• This port will operate in local port clocked mode, using the P0CLK clock input.
• The upstream port is connected in a common clock configuration to its link partner (e.g., root
port).
• The P0CLK clock input is driven by a stable reference clock prior to the EEPROM loading.
– Downstream ports: Ports 4, 6, 8 and 12 (x4)
• These ports will operate in global clocked mode, using the GCLK clock input.
• Ports 4, 6, and 8 are connected in a common clock configuration to their respective link partners.
• Port 12 is connected in a non-common configuration to its link partner.
Figure 26.2 shows the configuration.