IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 269 / 744

IDT Non-Transparent Switch Operation
PES32NT24xG2 User Manual 14 - 21 January 30, 2013
Notes
The interrupt sources each have a corresponding status bin in the NT Endpoint Interrupt Status
(NTINTSTS) register.
– When an interrupt source requests service, the corresponding bit in the NTINTSTS register is set.
– An interrupt source may be masked from generating an interrupt by setting the corresponding
mask bit in the NT Endpoint Interrupt Mask (NTINTMSK) register. By default, all interrupt sources
are masked.
– Once a bit corresponding to an interrupt source is set in the NTINTSTS register, interrupts asso-
ciated with that source are inhibited until the bit is cleared in the NTINTSTS register.
When an unmasked interrupt condition occurs, an MSI or interrupt message is generated by the NT
endpoint as described in Table 14.1. The removal of the interrupt condition occurs when unmasked status
bits causing the interrupt are masked or cleared.
– When an NT endpoint is configured to generate INTx messages, the INTx used (i.e., INTA, INTB,
etc.) depends on the programming of the Interrupt Pin (INTRPIN) register.
An MSI generated by the NT endpoint is always routed to the partition’s upstream port link.
– An MSI generated by the NT endpoint must not must not target memory ranges associated with
the upstream port’s PCI-to-PCI bridge function (e.g., memory base/limit registers) and/or DMA
function (e.g., BAR 0 aperture).
– An MSI generated by the NT endpoint never multicasted. Software must never configure the
address of an MSI generated by the NT function to fall within an enabled multicast BAR aperture
in the partition. Violating this requirement produces undefined results.
Virtual Channel Support
Virtual channel support for ports in the PES32NT24xG2 is described in section Virtual Channel Support
on page 14-21. The NT function contains a VC Capability Structure that provides architected port arbitration
and TC/VC mapping for VC0.
For port operating modes in which the NT function is function 0 of the port, the VC Capability Structure in
this function provides architected port arbitration and TC/VC mapping for all functions of the port. For port
operating modes in which the NT function is not function 0 of the port, the registers in the NT function’s VC
Capability Structure are ‘reserved’
1
and must not be programmed. In these modes, the VC Capability Struc-
ture in function 0 of the port provides architected port arbitration and TC/VC mapping for all functions of the
port, including the NT function.
Unmasked
Interrupt
EN Bit in
MSICAP
Register
INTXD Bit
in PCICMD
Register
Action
Asserted 1 X MSI message generated
0 0 Assert_INTx message request generated
0 1 None
Negated 1 X None
0 0 Deassert_INTx message request generated
0 1 None
Table 14.1 NT Endpoint Interrupts
1.
Reading from a reserved address returns and undefined value. Writes to a reserved address complete success-
fully but produce undefined behavior on the register.