IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 227 / 744

IDT SMBus Interfaces
PES32NT24xG2 User Manual 12 - 23 January 30, 2013
Notes
SMBus Transactions
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
See the SMBus Specification Version 2.0, August 3, 2000, SBS Implementers Forum for a detailed descrip-
tion of these transactions.
– Byte and Word Write/Read
– Block Write/Read
Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces
undefined results. Associated with each of the above transactions is a command code. The command code
format for operations supported by the slave SMBus interface is shown in Figure 12.9 and described in
Table 12.18.
Figure 12.9 Slave SMBus Command Code Format
Address
Bit
Address Bit Value
1 SSMBADDR[1]
2 SSMBADDR[2]
3 1
4 0
5 1
6 1
7 1
Table 12.17 Slave SMBus Address
Bit
Field
Name Description
0 END End of transaction indicator. Setting both START and END signifies a
single transaction sequence
0 - Current transaction is not the last read or write sequence.
1 - Current transaction is the last read or write sequence.
1 START Start of transaction indicator. Setting both START and END signifies
a single transaction sequence
0 - Current transaction is not the first of a read or write sequence.
1 - Current transaction is the first of a read or write sequence.
Table 12.18 Slave SMBus Command Code Fields
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
END START FUNCTION SIZE PEC