IDT Installation of the EB-LOGAN-23 Evaluation Board
89EB-LOGAN-23 Evaluation Board
2 - 11
February 16, 2011
Notes
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 2.12 is sampled by the
PES32NT24AG2 during a fundamental reset (while PERSTN is active). The boot configuration vector
defines the essential parameters for switch operation and is set using DIP switches S5, SW8, SW9, and
SW10 as defined in Table 2.13.
Stack
Ports Associated with the
Stack
Stack 0
0, 1, 2, 3
Stack 1
4, 5, 6, 7
Stack 2
8, 9, 10, 11, 12, 13, 14, 15
Stack 3
16, 17, 18, 19, 20, 21, 22, 23
Table 2.11 Ports in Each Stack
Signal
Description
GCLKFSEL
Global Clock Frequency Select.
This pin specifies the frequency of the GCLKP and
GCLKN signals.
Default: low
CLKMODE[1:0]
Clock Mode.
These pins specify the clocking mode used by switch ports. See
Table 2.5 for a definition of the encoding of these signals. The value of these signals may
be overridden by modifying the Port Clocking Mode (PCLKMODE) register.
Default: 0x0
RSTHALT
Reset Halt.
When this pin is asserted during a switch fundamental reset
sequence, the switch remains in a quasi-reset state with the Master and Slave SMBuses
active. This allows software to read and write registers internal to the device before normal
device operation begins. The device exits the quasi-reset state when the RSTHALT
bit is cleared in the SWCTL register by an SMBus master. Refer to section Switch Funda-
mental Reset on page 3-2 for further details.
Default: low
SSMBADDR[2:1]
Slave SMBus Address.
SMBus address of the switch on the slave SMBus.
Default: 0x3
SWMODE[3:0]
Switch Mode.
These pins specify the switch operating mode.
Default: 0x0
STK0CFG[1:0]
Stack 0 Configuration.
These pins select the configuration of stack 0 during a switch fun-
damental reset.
Default: 0x1
STK1CFG[1:0]
Stack 1 Configuration.
These pins select the configuration of stack 1 during a switch fun-
damental reset.
Default: 0x1
STK2CFG[4:0]
Stack 2 Configuration.
These pins select the configuration of stack 2 during a switch fun-
damental reset.
Default: 0x1
STK3CFG[4:0]
Stack 3 Configuration.
These pins select the configuration of stack 3 during a switch fun-
damental
reset
. Default: 0x1
Table 2.12 Boot Configuration Vector Signals
Summary of Contents for EB-LOGAN-23
Page 4: ...IDT Table of Contents EB LOGAN 23 Evaluation Board ii February 16 2011 Notes ...
Page 6: ...IDT List of Figures EB LOGAN 23 Evaluation Board iv February 16 2011 Notes ...
Page 8: ...IDT List of Tables VB64H16AG2 Validation Board Manual vi February 16 2011 Notes ...
Page 40: ...IDT Software For EB LOGAN 23 89EB LOGAN 23 Evaluation Board 3 2 February 16 2011 Notes ...
Page 41: ...Notes EB LOGAN 23 Evaluation Board 4 1 February 16 2011 Chapter 4 Schematics Schematics ...
