8. JTAG and Boundary Scan > Configuration Register Access (Revision A/B)
CPS-1848 User Manual
186
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
8.6.1
Configuration Register Access – Writes
When bit 0 of the data stream is 0, data shifted in after the address is written to the address specified in jtag_config_addr. The
TDO pin will transmit all 0s. Write timing is displayed in the following figure.
Figure 42: JTAG Write Access Timing Diagram
The CPS-1848 can report an unexpected termination of a register write using JTAG, and that JTAG sourced write data is not
on a 32-bit boundary – this applies to writes to configuration registers. The error code for this report is defined in
.
8.6.2
Configuration Register Access – Reads
When bit 0 of the data stream is 1, data shifted out is read from the address specified in jtag_config_addr. The TDI pin is not
used after the address is shifted in. Read timing is displayed in the following figure.
Figure 43: JTAG Read Access Timing Diagram
The read latency value is 16 JTAG clock cycles. This value applies to both full rate and half rate core
clock rates.
Shift_dr
Capture _dr
Shift_dr
Pause_dr
Exit1_dr
Exit2_dr
Update_dr
Exit1_dr
Exit2_dr
Pause_dr
Select_dr_scan
TAP controller
state
TDO
Z
Z
Z
Internal
address
Address
Internal
data
Data
Address
Data
TDI
Shift_dr
Capture_dr
Shift_dr
Pause_dr
Exit1_dr
Exit2_dr
Update_dr
Exit1_dr
Exit2_dr
Pause_dr
Select_dr_scan
TAP controller
state
TDI
Address
TDO
Z
Z
Z
Data
Read latency
Data 1
Internal
address
Address
Internal
data
Data
