Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
7 - 1
July 10, 2012
Chapter 7
Reference Clock
7 REFERENCE CLOCK
The CPS uses a reference clock (REF_CLK) to generate its RIO PHY and internal clocks. This section
outlines the definition of this clock and the auxiliary clocks used for testing.
7.1 REFERENCE CLOCK SPECIFICATION
The CPS internal timing is based on a AC coupled Reference Clock as specified below. CPS supports full
functionality when supplied with a reference clock of 156.25 MHz.
Figure 7.1 Reference Clock Representative Circuit
7.2 PLL
The device provides an internal PLL to create the 312.5MHz or half of that internal SYS_CLK that is used to
drive internal logic. The REF_CLK is multiplied by 4, 8 and 10 to generate the bit clocks needed for PHY
clocks. The resultant PHY_CLK is also divided by 5 for the byte time of the internal parallel data. If half
clock is applied to the reference clock, all the output clocks are changed to half frequency.
5686 drw07
REF_CLK_P
REF_CLK_N
REF_CLK
L
I
, CLK
C
I
, CLK
V
BIAS
, CLK
L
I
, CLK
C
I
, CLK
R
L
,CLK
R
L
,CLK
+
-
Internal
External
to Device
to Device
