IDT 89HPES48T12G2, User Manual

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IDT Reset and Initialization
PES48T12G2 User Manual 5 - 2 April 5, 2013
Notes As noted in Table 5.2, some of the initial values specified by the boot configuration vector may be over-
ridden by software, serial EEPROM, or an external SMBus device. The state of all of the boot configuration
signals in Table 5.2 sampled during a switch fundamental reset may be determined from the Boot Configu-
ration Status (BCVSTS) register.
Switch Fundamental Reset
A switch fundamental reset may be cold or warm. A cold switch fundamental reset occurs following a
device being powered-on and assertion of the global reset (PERSTN) signal. A warm switch fundamental
reset occurs when a switch fundamental reset is initiated while power remains applied. The PES48T12G2
behaves in the same manner regardless of whether the switch fundamental reset is cold or warm.
Signal
May Be
Overridden
Name/Description
GCLKFSEL N Global Clock Frequency Select.
This pin specifies the frequency of the GCLKP and GCLKN
signals.
CLKMODE[1:0] Y Clock Mode.
These pins specify the clocking mode used by switch ports.
See Table 4.1 for a definition of the encoding of these signals.
The value of these signals may be overridden by modifying
the Port Clocking Mode (PCLKMODE) register.
P01MERGEN N Ports 0 and 1 Merge.
This pin specifies whether ports 0 and 1 are merged.
P23MERGEN N Ports 2 and 3 Merge.
This pin specifies whether ports 2 and 3 are merged.
P45MERGEN N Ports 4 and 5 Merge.
This pin specifies whether ports 4 and 5 are merged.
P67MERGEN N Ports 6 and 7 Merge.
This pin specifies whether ports 6 and 7 are merged.
P89MERGEN N Ports 8 and 9 Merge.
This pin specifies whether ports 6 and 8 are merged.
P1213MERGEN N Ports 12 and 13 Merge.
This pin specifies whether ports 12 and 13 are merged.
RSTHALT Y Reset Halt.
When this pin is asserted during a switch fundamental reset
sequence, the PES48T12G2 remains in a reset state with the
Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal
device operation begins. The device exits the reset state
when the RSTHALT bit is cleared in the SWCTL register by
an SMBus master.
SSMBADDR[2,1] N Slave SMBus Address.
SMBus address of the switch on the slave SMBus.
SWMODE[3:0] N Switch Mode.
These pins specify the switch operating mode.
Table 5.2 Boot Configuration Vector Signals