IDT 89HPES48T12G2, User Manual

Page: 44 / 276

IDT Switch Core
PES48T12G2 User Manual 3 - 4 April 5, 2013
Notes Applying ordering rules at the output of the ingress buffer (i.e., before the crossbar) is done to ensure
that packets are ordered regardless of their destination port. This guarantees that the producer/consumer
model is met when the data transfer involves any number of peers.
Applying ordering rules at the output of the egress buffer is done to allow packets in the EFB to be re-
ordered for deadlock prevention and efficient transmission on the link without violating the PCIe ordering
rules. Without this ordering logic, packets in the EFB would need to be transmitted in the order they were
received by the EFB. If the oldest packet in the EFB lacked sufficient link credits for its departure, head-of-
line blocking would occur at the EFB. The presence of ordering logic at the EFB reliefs potential head-of-
line blocking by allowing other packets to be transmitted, as long as ordering rules are not violated.
Table 3.4 shows the ordering rules honored by the Switch Core. Note that the PES48T12G2 honors the
relaxed-ordering attribute in packets as shown in the table.
Arbitration
Packets stored in the ingress buffers are subject to arbitration as they are moved towards the egress
port. The switch core performs all packet arbitration functions in the switch. Architecturally, arbitration is
done at the egress ports. Each port has a dedicated arbitration configuration as programmed in the port’s
VC Capability Structure.
Packets undergo two levels of arbitration at an egress port:
– Port arbitration within a VC
– VC arbitration for access to the egress link
Figure 3.2 shows the architectural model of arbitration. The following sub-sections describe arbitration in
detail.
Note: There are no ports 10 and 11 in this device.
Row Pass Column?
Posted
Request Non-Posted Request
Completion
Memory
Write or
Message
Request
Read
Request
IO or
Configur
ation
Write
Request
Read
Comple-
tion
IO or
Configur
ation
Write
Comple-
tion
Posted
Request
Memory
Write or
Message
Request
No Yes Yes Yes Yes
Non Posted
Request
Read
Request
No No No Yes Yes
IO or Config-
uration Write
Request
No No No Yes Yes
Completion
Request
Read Com-
pletion
‘Yes’ if packet
has RO bit
set; Else ‘No’
Yes Yes No No
IO or Config-
uration Write
Completion
Yes Yes No No
Table 3.4 Packet Ordering Rules in the PES48T12G2