IDT 89HPES48T12G2, User Manual

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IDT Register Organization
PES48T12G2 User Manual 14 - 2 April 5, 2013
Notes The entire PES48T12G2 global address space may be accessed using PCI configuration requests from
any PES48T12G2 PCI function.
– Located in each PCI function is a Global Address Space Access Address (GASAADDR) and
Global Address Space Access Data (GASADATA) register.
– The DWord address of the global address space register to be accessed is written to the Address
(ADDR) field in the GASAADDR register. When a read is performed to the Data (DATA) field in the
GASADATA register, the value of the corresponding global address space register selected by the
ADDR field is returned. When a write is performed to the DATA field, the value of the corre-
sponding global address space register selected by the ADDR field is updated with the value
written.
– Any register in the entire device may be accessed using the GASAADDR and GASADATA regis-
ters.
Access to the global address space registers may be done via PCI configuration accesses, via SMBus,
or via serial EEPROM. SMBus or serial EEPROM accesses are not affected by the global address space
protection register.
Partial-Byte Access to Word and DWord Registers
Configuration registers in the switch have different sizes (e.g., Byte, Word, DWord). Registers should be
accessed with byte-enables that correspond to their native size or a size of one DWord. For example, a
Byte register should be read or written with only one byte enable set, or with all four byte enables set. A
DWord register should be read or written with all the byte-enables set.
Register Side-Effects
There are software visible configuration registers that have a side-effect action when written and this
side-effect action may affect the ability of the switch to respond with a completion. A configuration write to
such a register always returns a completion to the link partner before the side-effect action is performed.
This is implemented by delaying the side-effect action by 1ms following generation of the completion. If
the completion is not accepted by the link partner in this time interval, then the completion will be lost.
The following registers, when written, have a side-effect action delay.
– PCI-to-PCI Bridge Function Registers
• PHYLSTATE0.FLRET
– Switch Configuration and Status Registers
• SWPORTxCTL.MODE
Limitations
Due to a switch design limitation, a PCI Express configuration request must never set the FLRET bit in
the PHYLSTATE0 register of a partition’s upstream port that is crosslinked. This operation is not supported
and will result in the completion associated with that request to be lost.
Address Maps
This section describes the address maps for regions of the global address space outlined in Table 14.1.
Reserved address ranges are outlined in Table 14.1. Reading from a reserved address range returns and
undefined value. Writes to a reserved address range complete successfully and have an undefined
behavior.
PCI-to-PCI Bridge Registers
This section outlines the configuration space associated with PCI-to-PCI bridges. These registers are
accessible as function 0 when the port is configured in the following modes.
– Upstream switch port
– Downstream switch port