IDT 89HPES34H16, User Manual, Page: 75 / 182

IDT SMBus Interfaces
PES34H16 User Manual 6 - 17 October 30, 2008
Notes
I/O Expander 10
Slave SMBus Interface
The slave SMBus interface provides the PES34H16 with a configuration, management and debug inter-
face.
Using the slave SMBus interface, an external master can read or write any software visible register in
the device.
Initialization
Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page
3-5).
During the fundamental reset initialization sequence, the slave SMBus address is initialized. The
address is specified by the SSMBADDR[5,3:1] signals as shown in Table 6.14.
SMBus I/O
Expander
Bit
Type Signal Description
0 (I/O-0.0)
1
1.
I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
- Unused
1 (I/O-0.1) I P1PWRGDN Port 1 power good input
2 (I/O-0.2) I P2PWRGDN Port 2 power good input
3 (I/O-0.3) I P3PWRGDN Port 3 power good input
4 (I/O-0.4) I P4PWRGDN Port 4 power good input
5 (I/O-0.5) I P5PWRGDN Port 5 power good input
6 (I/O-0.6) I P6PWRGDN Port 6 power good input
7 (I/O-0.7) I P7PWRGDN Port 7 power good input
8 (I/O-1.0) I P8PWRGDN Port 8 power good input
9 (I/O-1.1) I P9PWRGDN Port 9 power good input
10 (I/O-1.2) I P10PWRGDN Port 10 power good input
11 (I/O-1.3) I P11PWRGDN Port 11 power good input
12 (I/O-1.4) I P12PWRGDN Port 12 power good input
13 (I/O-1.5) I P13PWRGDN Port 13 power good input
14 (I/O-1.6) I P14PWRGDN Port 14 power good input
15 (I/O-1.7) I P15PWRGDN Port 15 power good input
Table 6.13 I/O Expander 10 Signals
Address
Bit
Address Bit Value
1 SSMBADDR[1]
2 SSMBADDR[2]
3 SSMBADDR[3]
Table 6.14 Slave SMBus Address When a Static Address is Selected (Part 1 of 2)