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IDT   Clocking, Reset, and Initialization

Clock Operation

PES34H16 User Manual

3 - 9

October 30, 2008

Notes

Power Enable Controlled Reset Output

In this mode a downstream port reset output state is controlled as a side effect of slot power being

turned on or off. The operation of this mode is illustrated in Figure 3.6. A downstream port’s slot power is
controlled by the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register

Figure 3.6  Power Enable Controlled Reset Output Mode Operation

While slot power is disabled, the corresponding downstream port reset output is asserted. 

When slot power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is

asserted and then power to the slot is enabled and the corresponding downstream port reset output is
negated. The time between the assertion of the PxPEP signal and the negation of the PxRSTN signal is
controlled by the value in the Slot Power to Reset Negation (PWR2RST) field in the HPCFGCTL register.

While slot power is enabled, the corresponding downstream port reset output is negated.

When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset

output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.

Power Good Controlled Reset Output

As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is

controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on
the power good state of the slot’s power supply. The operation of this mode is illustrated in Figure 3.7.

Figure 3.7  Power Good Controlled Reset Output Mode Operation

The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that

when power is enabled, the negation of the corresponding port reset output occurs as a result of and after
assertion of the slot’s Power Good (PxPWRGDN) signal is observed. The time between the assertion of the
PxPWRGDN signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to
Reset Negation (PWR2RST) field in the HPCFGCTL register.

When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset

output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.

If at any point while a downstream port is not being reset (i.e., PxRSTN is negated) a power fault is

detected (i.e., PxPWRGDN is negated), then the corresponding port reset output is immediately asserted.

PxPEP

PxRSTN

T

PWR2RST

T

RST2PWR

PxPEP

PxPWRGDN

T

PWR2RST

PxRSTN

T

RST2PWR

Summary of Contents for 89HPES34H16

Page 1: ...8 6024 Silver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2008 Integrated Device Technology Inc IDT 89HPES34H16 PCI Express Switch...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...eneral Purpose I O describes how the 32 General Purpose I O GPIO pins may be individually configured as general purpose inputs general purpose outputs or alternate functions Chapter 6 SMBus Interfaces...

Page 4: ...BCxD ABCyD and ABCzD The compressed notation ABC x y D refers to ABCxD ABC x 1 D ABC x 2 D ABCyD Data Units The following data unit terminology is used in this document In quadwords bit 63 is always t...

Page 5: ...Write RCW Software can read the register bits with this attribute Reading the value will automatically cause the register bits to be reset to zero Writes cause the register bits to be modified Reserv...

Page 6: ...time out to end to end parity error October 30 2008 Updated the following Description fields LDIS in the PCIELCTL register INTXD in PCICMD register changed RO to RW for bits 10 9 in the HPCFGCTL regi...

Page 7: ...vision ID 1 4 JTAG ID 1 4 SSID SSVID 1 4 Device Serial Number Enhanced Capability 1 4 Pin Description 1 5 Pin Characteristics 1 12 Port Configuration 1 15 Disabled Ports 1 16 Upstream Port Failover In...

Page 8: ...ion 5 2 SMBus Interfaces Introduction 6 1 Master SMBus Interface 6 2 Initialization 6 2 Serial EEPROM 6 2 I O Expanders 6 6 Slave SMBus Interface 6 17 Initialization 6 17 SMBus Transactions 6 18 Power...

Page 9: ...mber Enhanced Capability 9 45 PCI Express Virtual Channel Capability 9 46 Power Budgeting Enhanced Capability 9 57 Switch Control and Status Registers 9 59 Internal Switch Error Control and Status Reg...

Page 10: ...IDT Table of Contents PES34H16 User Manual iv October 30 2008 Notes...

Page 11: ...xpander 6 Signals 6 14 Table 6 10 I O Expander 7 Signals 6 15 Table 6 11 I O Expander 8 Signals 6 15 Table 6 12 I O Expander 9 Signals 6 16 Table 6 13 I O Expander 10 Signals 6 17 Table 6 14 Slave SMB...

Page 12: ...IDT List of Tables PES34H16 User Manual vi October 30 2008 Notes...

Page 13: ...3 Figure 4 5 Merged Port Lane Reversal for Maximum Link Width of x8 MAXLNKWDTH 5 0 0x8 4 4 Figure 4 6 PES34H16 ASPM Link Sate Transitions 4 6 Figure 6 1 SMBus Interface Configuration Examples 6 1 Fig...

Page 14: ...0 1 Diagram of the JTAG Logic 10 1 Figure 10 2 State Diagram of PES34H16 s TAP Controller 10 2 Figure 10 3 Diagram of Observe only Input Cell 10 6 Figure 10 4 Diagram of Output Cell 10 6 Figure 10 5 D...

Page 15: ...BASE Expansion ROM Base Address Register 0x038 9 20 GPECTL General Purpose Event Control 0x450 9 70 GPESTS General Purpose Event Status 0x454 9 72 GPIOCFG General Purpose I O Configuration 0x41C 9 63...

Page 16: ...er Management Capabilities 0x0C0 9 35 PMCSR PCI Power Management Control and Status 0x0C4 9 36 PMLIMIT Prefetchable Memory Limit Register 0x026 9 19 PMLIMITU Prefetchable Memory Limit Upper Register 0...

Page 17: ...tatus 0x218 9 50 VCR0TBL0 VC Resource 0 Arbitration Table Entry 0 0x230 9 52 VCR0TBL1 VC Resource 0 Arbitration Table Entry 1 0x234 9 53 VCR0TBL2 VC Resource 0 Arbitration Table Entry 2 0x238 9 53 VCR...

Page 18: ...IDT Register List PES34H16 User Manual xii October 30 2008 Notes...

Page 19: ...ugh switch architecture Support for Max Payload Size up to 2048 bytes Supports two virtual channels and eight traffic classes PCI Express Base Specification Revision 1 1 compliant Flexible Architectur...

Page 20: ...Ingress Port 6 Port 7 Bifurcating PCI Express Stack 4 Ingress Port 8 Port 9 Bifurcating PCI Express Stack 5 Ingress Port 10 Port 11 Bifurcating PCI Express Stack 6 Ingress Port 12 Port 13 Bifurcating...

Page 21: ...PE1RN 3 PCIe Switch SerDes Input PE1TP 0 PE1TN 0 PE1TP 3 PE1TN 3 Port 1 PE2RP 0 PE2RN 0 PE2RP 3 PE2RN 3 PE2TP 0 PE2TN 0 PE2TP 3 PE2TN 3 PE5RP 0 PE5RN 0 PE5RP 3 PE5RN 3 PE5TP 0 PE5TN 0 PE5TP 3 PE5TN 3...

Page 22: ...s capability the SSID and SSVID fields in the Subsystem ID and Subsystem Vendor ID SSIDSSVID register must be initialized with the appropriate ID values the Next Pointer NXTPTR field in one of the oth...

Page 23: ...al Data Receive Differential PCI Express receive pairs for port 2 PE2TP 3 0 PE2TN 3 0 O PCI Express Port 2 Serial Data Transmit Differential PCI Express transmit pairs for port 2 PE3RP 3 0 PE3RN 3 0 I...

Page 24: ...ress Port 12 Serial Data Transmit Differential PCI Express trans mit pair for port 12 PE13RP 0 PE13RN 0 I PCI Express Port 13 Serial Data Receive Differential PCI Express receive pair for port 13 PE13...

Page 25: ...General Purpose I O This pin can be configured as a general purpose I O pin GPIO 2 I O General Purpose I O This pin can be configured as a general purpose I O pin GPIO 3 I O General Purpose I O This...

Page 26: ...P8RSTN Alternate function pin type Output Alternate function Reset output for downstream port 8 GPIO 14 I O General Purpose I O This pin can be configured as a general purpose I O pin Alternate functi...

Page 27: ...in name IOEXPINTN2 Alternate function pin type Input Alternate function SMBus I O expander interrupt 2 GPIO 24 I O General Purpose I O This pin can be configured as a general purpose I O pin Alternate...

Page 28: ...n P01MERGEN I Port 0 and 1 Merge P01MERGEN is an active low signal It is pulled low internally via a 251K ohm resistor When this pin is low port 0 is merged with port 1 to form a single x8 port The Se...

Page 29: ...r port 0 selected as the upstream port 0xB Normal switch mode with Serial EEPROM initialization and upstream port failover port 2 selected as the upstream port 0xC through 0xF Reserved Signal Type Nam...

Page 30: ...ower used by the digital power of the SerDes VDDAPE I PCI Express Analog Power PCI Express analog power used by the PLL and bias generator VSS I Ground VTTPE PCI Express Serial Data Transmit Terminati...

Page 31: ...N 0 O PE6TP 0 O PE7RN 0 I PE7RP 0 I PE7TN 0 O PE7TP 0 O PE8RN 0 I PE8RP 0 I PE8TN 0 O PE8TP 0 O PE9RN 0 I PE9RP 0 I PE9TN 0 O PE9TP 0 O PE10RN 0 I PE10RP 0 I PE10TN 0 O PE10TP 0 O PE11RN 0 I PE11RP 0...

Page 32: ...1 MSMBDAT I O STI SSMBADDR 5 3 1 I pull up SSMBCLK I O STI SSMBDAT I O STI General Purpose I O GPIO 31 0 I O LVTTL pull up System Pins CCLKDS I LVTTL Input pull up CCLKUS I pull up MSMBSMODE I pull do...

Page 33: ...or write transactions to device y on the PES34H16 s virtual PCI bus are treated by the upstream port port 0 as unsupported requests i e the device no longer exists This renders the registers in port y...

Page 34: ...mple if port 5 is disabled the P45MERGEN has no effect on the PES34H16 Configuration read or write transactions to a device that corresponds to a disabled port on the PES34H16 s virtual PCI bus are tr...

Page 35: ...f the upstream port failover architecture is shown in Figure 2 1 Figure 2 1 Upstream Port Failover Architecture Stack 0 is always associated with the upstream port In normal mode SerDes lanes associat...

Page 36: ...nd the upstream port is config ured to operate in x4 bifurcated mode then ports 1 and 3 operate as normal While upstream port failover mode disables port 2 in bifurcated mode it has no effect on the o...

Page 37: ...o effect on system operation when an upstream port failover switch mode has not been selected during a fundamental reset Static Upstream Port Failover A static upstream port failover requires a fundam...

Page 38: ...odified during an upstream port failover i e failover requests are not queued Signal Initiated Failover An upstream port failover may be initiated by a change in the state of the Upstream Port Select...

Page 39: ...ecomes the one that is not selected by the CUSP field in the USPFSTS register For example if the current upstream port is port 0 then the new upstream port following the failover is port 2 When the co...

Page 40: ...IDT Upstream Port Failover PES34H16 User Manual 2 6 October 30 2008 Notes...

Page 41: ...s the 250 MHz clock generated by the PLL is bypassed and the reference clock input on REFCLKP 0 REFCLKN 0 is used for the core logic Clock Operation When the CCLKUS and CCLKDS pins are asserted they i...

Page 42: ...Spectrum Clock Figure 3 3 Common Clock on Upstream Non Common Clock on Downstream must disable Spread Spectrum Clock PES34H16 Port 0 CCLKDS CCLKUS Root Complex Hi Low Clock Generator Clock Generator...

Page 43: ...al serial EEPROM and slave SMBus interface may be used to override the function of some of the signals in the boot configuration vector during a fundamental reset The signals that may be over ridden a...

Page 44: ...anes associated with port 5 become lanes 4 through 7 of port 4 PERSTN I Fundamental Reset Assertion of this signal resets all logic inside the PES34H16 and initiates a PCI Express fundamental reset RS...

Page 45: ...of the clearing of the fundamental reset condition all of the stacks are able to process configuration transactions and respond to these transactions with a configuration request retry status completi...

Page 46: ...n When a fundamental reset occurs all of the GPIO pins default to GPIO inputs Therefore the downstream port resets are tri stated A system designer should use a pull down on these signals if they are...

Page 47: ...the serial EEPROM and the Disable Hot Reset Serial EEPROM Initialization DHRSTSEI bit is not set in the Switch Control SWCTL register then the contents of the serial EEPROM are read and the appropria...

Page 48: ...SRESET bit in a downstream port s i e port 0 Bridge Control Register BCTRL When a downstream secondary bus reset occurs the following sequence is executed 1 If the corresponding downstream port s link...

Page 49: ...n the Reset Negation to Slot Power RST2PWR field in the HPCFGCTL register Power Good Controlled Reset Output As in the Power Enable Controlled Reset mode in this mode a downstream port reset output st...

Page 50: ...2008 Notes Since the PxPWRGDN signal is an I O expander input it may not be possible to meet a profile s power level invalid to reset asserted timing specification i e PxPWRGDN to PxRSTN Systems that...

Page 51: ...ld in a port s PCI Express Link Capabilities PCIELCAP register contains the maximum link width of the port This field is of RWL type and may be modified when the REGUNLOCK bit is set in the SWCTL regi...

Page 52: ...PExRP 1 PExRP 2 PExRP 3 PES34H16 lane 0 lane 1 a x2 Port without lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PES34H16 lane 1 lane 0 b x2 Port with lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PES34...

Page 53: ...2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES34H16 lane 0 d x1 Port with lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES34H16 lane 0 lane 1 lane 2 lane 3 a x4 Port wi...

Page 54: ...tate PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES34H16 lane 0 lane 1 lane 2 lane 3 lane 4 lane 5 lane 6 lane 7 a x8 Port without lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PE...

Page 55: ...Capabilities PCIEDCAP register of that port Byte 0 bits 7 0 of the message payload are written to the Captured Slot Power Limit Scale CSPLS field Byte 1 bits 1 0 of the message payload are written to...

Page 56: ...te from its link partner Note that L1 entry requests are only made by the PES34H16 upstream port If the link partner acknowledges the transition then the L1 state is entered Otherwise the L0s state is...

Page 57: ...stream port 2 Output 8 P3RSTN Reset output for downstream port 3 Output 9 P4RSTN Reset output for downstream port 4 Output 10 P5RSTN Reset output for downstream port 5 Output 11 P6RSTN Reset output fo...

Page 58: ...is register corresponds to the value of the pin irrespective of whether the pin is configured as a GPIO input GPIO output or alternate function GPIO Pin Configured as an Output When configured as an o...

Page 59: ...r split configuration Figure 6 1 SMBus Interface Configuration Examples In the unified configuration shown in Figure 6 1 a the master and slave SMBuses are tied together and the PES34H16 acts both as...

Page 60: ...serial EEPROM initialization The address used by the SMBus interface to access the serial EEPROM is specified by the MSMBADDR 4 1 signals as shown in Table 6 1 Device Initialization from a Serial EEP...

Page 61: ...his value with two lower zero bits appended The next field is the TYPE field that indicates the type of the configuration block For single double word initialization sequence this value is always 0x0...

Page 62: ...done sequences Figure 6 3 Configuration Done Sequence Format The checksum in the configuration done sequence enables the integrity of the serial EEPROM initializa tion to be verified Since uninitializ...

Page 63: ...e EEPROM is not busy then the read operation may be initiated by performing a write to the Data DATA field When the serial EEPROM read operation completes the Done DONE bit in the EEPROMINTF register...

Page 64: ...to I O expanders I O expanders zero through seven are used to provide general hot plug I O signals I O expander eight provides link status outputs while I O expander nine provides link activity LED s...

Page 65: ...en SMBus write transactions are issued to the corresponding I O expander by the PES34H16 to configure the device This configuration initializes the direction of each I O expander signal and sets outpu...

Page 66: ...egister 5 no inversion in IO 1 Write the configuration value to select all outputs in the lower eight I O expander bits i e I O 0 0 through I O 0 7 to I O expander register 6 Write the configuration v...

Page 67: ...ted on the master SMBus in a fair manner This guarantees that all I O expanders have equal service latencies Any errors detected during I O expander SMBus read or write transactions is reflected in th...

Page 68: ...required by all of the PES34H16 hot plug I O expanders Therefore it is recommended that a MAX7313 be used instead The MAX7313 is software and pin compatible with the PCA9555 I O expander outputs are...

Page 69: ...I P4PDN Port 4 presence detect input 10 I O 1 2 I P4PFN Port 4 power fault input 11 I O 1 3 I P4MRLN Port 4 manually operated retention latch MRL input 12 I O 1 4 O P4AIN Port 4 attention indicator ou...

Page 70: ...ion push button input 1 I O 0 1 I P6PDN Port 6 presence detect input 2 I O 0 2 I P6PFN Port 6 power fault input 3 I O 0 3 I P6MRLN Port 6 manually operated retention latch MRL input 4 I O 0 4 O P6AIN...

Page 71: ...11 presence detect input 10 I O 1 2 I P11PFN Port 11 power fault input 11 I O 1 3 I P11MRLN Port 11 manually operated retention latch MRL input 12 I O 1 4 O P11AIN Port 11 attention indicator output 1...

Page 72: ...sh button input 1 I O 0 1 I P13PDN Port 13 presence detect input 2 I O 0 2 I P13PFN Port 13 power fault input 3 I O 0 3 I P13MRLN Port 13 manually operated retention latch MRL input 4 I O 0 4 O P13AIN...

Page 73: ...0 7 O P14ILOCKP Port 14 electromechanical interlock 8 I O 1 0 I Unused 9 I O 1 1 I Unused 10 I O 1 2 I Unused 11 I O 1 3 I Unused 12 I O 1 4 O Unused 13 I O 1 5 O Unused 14 I O 1 6 O Unused 15 I O 1 7...

Page 74: ...O 0 1 O P1ACTIVENN Port 1 active status output 2 I O 0 2 O P2ACTIVENN Port 2 active status output 3 I O 0 3 O P3ACTIVENN Port 3 active status output 4 I O 0 4 O P4ACTIVENN Port 4 active status output...

Page 75: ...for PCA9555 port x I O pin y Unused 1 I O 0 1 I P1PWRGDN Port 1 power good input 2 I O 0 2 I P2PWRGDN Port 2 power good input 3 I O 0 3 I P3PWRGDN Port 3 power good input 4 I O 0 4 I P4PWRGDN Port 4...

Page 76: ...ibed in Table 6 15 Figure 6 7 Slave SMBus Command Code Format 4 0 5 SSMBADDR 5 6 1 7 1 Bit Field Name Description 0 END End of transaction indicator Setting both START and END signifies a single trans...

Page 77: ...tion 0 Packet error checking disabled for the current SMBus transaction 1 Packet error checking enabled for the current SMBus transaction Byte Positio n Field Name Description 0 CCODE Command Code Sla...

Page 78: ...r Middle When set the byte enable for bits 23 16 of the data word is enabled 3 BEUU Read Write Byte Enable Upper When set the byte enable for bits 31 24 of the data word is enabled 4 OP Read Write CSR...

Page 79: ...ROM on the Master SMBus when the USA bit is set in the CMD field Bit zero must be zero and thus the 7 bit address must be left justified 4 ADDRL Address Low Lower 8 bits of the Serial EEPROM byte to a...

Page 80: ...AERR RC Lost Arbitration Error This bit is set if the master SMBus interface loses 16 consecutive arbitration attempts when accessing the serial EEPROM This bit has the same function as the LAERR bit...

Page 81: ...6 Slave SMBus Address Rd ADDRU A BYTCNT 5 A EEADDR CMD status A A A N DATA ADDRU A P ADDRL A S PES34H16 Slave SMBus Address Wr A N CCODE START END P PES34H16 not ready with data S PES34H16 Slave SMBus...

Page 82: ...ART Word S PES34H16 Slave SMBus Address Rd DATALM DATALL A N P P S PES34H16 Slave SMBus Address Wr A A ADDRU A CCODE END Byte P A S PES34H16 Slave SMBus Address Wr A CCODE Byte A P A S PES34H16 Slave...

Page 83: ...ages are received then the entire device is placed into a low power state The PES34H16 supports the following device power management states D0 Uninitialized D0 Active D3Hot and D3Cold A power managem...

Page 84: ...his includes both the case when the downstream port is in the D3hot state or the entire switch is in the D3hot state The generation of a PME message by downstream ports necessitates the implementation...

Page 85: ...ers in this capability should be initialized and the Next Pointer NXTPTR field in the PCI Express VC Enhanced Capability Header PCIEVCECAP register should be initialized to point to the power budgetin...

Page 86: ...IDT Power Management PES34H16 User Manual 7 4 October 30 2008 Notes...

Page 87: ...e upstream port serves as the add in card s PCIe interface In this application the upstream port may be hot plugged into a slot on the main system Finally Figure 8 3 illustrates the use of the PES34H1...

Page 88: ...lot is implemented or on the add in board When located on the add in board state changes are communicated between the hot plug controller asso ciated with the slot and the add in card via hot plug mes...

Page 89: ...or 100 to 150 ms and then transitions back to negated When the Toggle Electromechanical Interlock Control TEMICTL bit in the HPCFGCTL register is set writing a one to the EIC bit inverts the state of...

Page 90: ...ed hot plug interrupt is generated the action taken is determined by the MSI Enable EN bit in the MSI Capability MSICAP register and the Interrupt Disable INTXD bit in the PCI Command PCICMD register...

Page 91: ...of the enhanced hot plug signalling mechanism in the form of a pseudo logic diagram Logic gates in this diagram are intended for conveying general concepts and not for direct implementation Figure 8 4...

Page 92: ...lerate a precharge voltage Since no clock is present during physical connection the device will maintain all outputs in a high impedance state even when no clock is present The I O cells meet VI requi...

Page 93: ...s a result of hot plug events the downstream ports contain an MSI capability structure which is not present in the upstream port PCIe configuration reads to an upstream port offset not defined in Tabl...

Page 94: ...wer Budgeting Enhanced Capability PCIe Virtual Channel Enhanced Capability Device Serial Number Enhanced Capability Advanced Error Reporting Enhanced Capability 0x000 0x040 0x0D0 0x0F0 Type 1 Configur...

Page 95: ...14 on page 9 15 0x018 Byte P0_PBUSN PBUSN Primary Bus Number Register 0x018 on page 9 15 0x019 Byte P0_SBUSN SBUSN Secondary Bus Number Register 0x019 on page 9 16 0x01A Byte P0_SUBUSN SUBUSN Subordin...

Page 96: ...ge 9 34 0x072 Word P0_PCIELSTS2 PCIELSTS2 PCI Express Link Status 2 0x072 on page 9 34 0x0C0 DWord P0_PMCAP PMCAP PCI Power Management Capabilities 0x0C0 on page 9 35 0x0C4 DWord P0_PMCSR PMCSR PCI Po...

Page 97: ...page 9 50 0x220 DWord P0_VCR1CTL VCR1CTL VC Resource 1 Control 0x220 on page 9 51 0x224 DWord P0_VCR1STS VCR1STS VC Resource 1 Status 0x224 on page 9 52 0x230 DWord P0_VCR0TBL0 VCR0TBL0 VC Resource 0...

Page 98: ...on page 9 63 0x41C DWord GPIOCFG GPIOCFG General Purpose I O Configuration 0x41C on page 9 63 0x420 DWord GPIOD GPIOD General Purpose I O Data 0x420 on page 9 64 0x424 DWord SMBUSSTS SMBUSSTS SMBus S...

Page 99: ...e 9 77 0x74C Dword P0_SWPECNT SWPECNT Switch Parity Error Count 0x74C on page 9 77 0x754 Dword P0_SWTOSTS SWTOSTS Switch Time Out Status 0x754 on page 9 77 0x758 Dword P0_SWTORCTL SWTORCTL Switch Time...

Page 100: ...14 on page 9 15 0x018 Byte Px_PBUSN PBUSN Primary Bus Number Register 0x018 on page 9 15 0x019 Byte Px_SBUSN SBUSN Secondary Bus Number Register 0x019 on page 9 16 0x01A Byte Px_SUBUSN SUBUSN Subordin...

Page 101: ...06A Word Px_PCIEDSTS2 PCIEDSTS2 PCI Express Device Status 2 0x06A on page 9 34 0x06C DWord Px_PCIELCAP2 PCIELCAP2 PCI Express Link Capabilities 2 0x06C on page 9 34 0x070 Word Px_PCIELCTL2 PCIELCTL2 P...

Page 102: ...pabilities 0x180 on page 9 46 0x184 Dword Px_SNUMLDW SNUMLDW Serial Number Lower Doubleword 0x184 on page 9 46 0x188 Dword Px_SNUMUDW SNUMUDW Serial Number Upper Doubleword 0x188 on page 9 46 0x200 DW...

Page 103: ...r Budgeting Data Value 7 0 0x300 on page 9 58 0x31C Dword Px_PWRBDV7 PWRBDV 7 0 Power Budgeting Data Value 7 0 0x300 on page 9 58 0x740 Dword Px_SWPECTL SWPECTL Switch Parity Error Control 0x740 on pa...

Page 104: ...ry space 2 BME RW 0x0 Bus Master Enable When this bit is cleared the bridge does not issue requests e g memory I O and MSIs since they are in band writes on behalf of subordinate devices and responds...

Page 105: ...primary interface 15 11 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 2 0 Reserved RO 0x0 Reserved field 3 INTS RO 0x0 INTx Status This bit is set when an INTx int...

Page 106: ...of the state of the PERRE bit in the PCI Command register Bit Field Field Name Type Default Value Description 7 0 RID RWL Revision ID This field contains the revision identification number for the de...

Page 107: ...th a sin gle function bridge layout Bit Field Field Name Type Default Value Description 7 0 BIST RO 0x0 BIST This value indicates that the bridge does not implement BIST Bit Field Field Name Type Defa...

Page 108: ...ster is used to record the bus number of the highest num bered PCI bus segment which is behind or subordinate to the bridge Bit Field Field Name Type Default Value Description 7 0 SLTIMER RO 0x0 Secon...

Page 109: ...Master Data Parity Error This bit is controlled by the Parity Error Response Enable bit in the Bridge Control register If the Parity Response Enable bit is cleared then this bit is never set Otherwise...

Page 110: ...o control the forwarding of non prefetchable trans actions between the primary and secondary interfaces of the bridge This field contains A 31 20 of the highest address with A 19 0 assumed to be 0xF_F...

Page 111: ...ld contains A 31 20 of the highest memory address with A 19 0 assumed to be 0xF_FFFF that is below the primary interface of the bridge PMLIMITU specifies the remaining bits Bit Field Field Name Type D...

Page 112: ...Bit Field Field Name Type Default Value Description 7 0 CAPPTR RWL 0x40 Capabilities Pointer This field specifies a pointer to the head of the capabilities structure Bit Field Field Name Type Default...

Page 113: ...interface of the bridge 1 SERRE RW 0x0 System Error Enable This bit controls forwarding of ERR_COR ERR_NONFATAL ERR_FATAL from the sec ondary interface of the bridge to the primary interface Note that...

Page 114: ...it Field Field Name Type Default Value Description 7 0 CAPID RO 0x10 Capability ID The value of 0x10 identifies this capability as a PCI Express capability structure 15 8 NXTPTR RWL 0xC0 Next Pointer...

Page 115: ...e L0s state to the L0 state The value is hard wired to 0x0 as this field does not apply to a switch 11 9 E1AL RO 0x0 Endpoint L1 Acceptable Latency This field indicates the acceptable total latency th...

Page 116: ...1x 0 001x 31 28 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 0 CEREN RW 0x0 Correctable Error Reporting Enable This bit controls reporting of correctable errors 1...

Page 117: ...tional effect on the behavior of the bridge 15 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 0 CED RW1C 0x0 Correctable Error Detected This bit indicates the statu...

Page 118: ...rate reference clock is used When separate clocks are used 1 s to 2 s is reported with a read only value of 0x5 When a common clock is used 256 ns to 512 ns is reported with a read only value of 0x3 1...

Page 119: ...rt 14 0xE Port 15 0xF Port Number This field indicates the PCI express port num ber for the corresponding link Bit Field Field Name Type Default Value Description 1 0 ASPM RW 0x0 Active State Power Ma...

Page 120: ...iguration When set this bit indicates that this component and the component at the opposite end of the link are operating with a distributed common reference clock 7 ESYNC RW 0x0 Extended Sync When se...

Page 121: ...is set when a Power Con troller is implemented for the port This bit is read only and has a value of zero when the SLOT bit in the PCIECAP register is cleared 2 MRLP RWL 0x0 MRL Sensor Present This b...

Page 122: ...en or when the link transi tions from a non DL_Up status to a DL_Up status This bit is read only and has a value of zero when the SLOT bit in the PCIECAP register is cleared 17 EIP RWL 0x0 Electromech...

Page 123: ...RW 0x0 Presence Detected Changed Enable This bit when set enables the generation of a Hot Plug interrupt or wake up event on a presence detect change event 4 CCIE RW 0x0 Command Complete Interrupt En...

Page 124: ...ed in the PCIESCAP register 0x0 on Power on 0x1 off Power off 11 EIC RW 0x0 Electromechanical Interlock Control This field always returns a value of zero when read If an electromechanical interlock is...

Page 125: ...ed 0x1 open MRL open 6 PDS RO 0x1 Presence Detect State This bit indicates the presence of a card in the slot corresponding to the port and reflects the state of the Presence Detect status 0x0 empty S...

Page 126: ...2 0x078 Bit Field Field Name Type Default Value Description 15 0 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 31 0 Reserved RO 0x0 Reserved field Bit Field Field...

Page 127: ...ce with version two of the specification Complies with version the PCI Bus Power Management Inter face Specification Revision 1 2 19 PMECLK RO 0x0 PME Clock Does not apply to PCI Express 20 Reserved R...

Page 128: ...t is set PME message genera tion is enabled for the port If a hot plug wakeup event is desired when exiting the D3cold state then this bit should be set during serial EEPROM initialization A hot reset...

Page 129: ...rite transaction The PES34H16 assumes that all downstream port gener ated MSIs are targeted to the root and routes these trans actions to the upstream port Configuring the address contained in a downs...

Page 130: ...6 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 7 0 CAPID RO 0xD Capability ID The value of 0xD identifies this capability as a SSID SSVID capability structure 15...

Page 131: ...inted to by the ECFGADDR register A write to this field will update the contents of the configuration space register pointed to by the ECFGADDR register with the value written For both reads and write...

Page 132: ...isoned TLP is detected 13 FCPERR RW1C 0x0 Sticky Flow Control Protocol Error Status This bit is set when a flow control protocol error is detected 14 COMPTO RO 0x0 Completion Time out Status A switch...

Page 133: ...0 Sticky Flow Control Protocol Error Mask When this bit is set the corresponding bit in the AERUES register is masked When a bit is masked in the AERUES register the corresponding event is not logged...

Page 134: ...reported as an uncorrect able error 5 SDOENERR RW 0x1 Sticky Surprise Down Error Status If the corresponding event is not masked in the AERUEM register then when the event occurs this bit controls the...

Page 135: ...Sticky ECRC Severity If the corresponding event is not masked in the AERUEM register then when the event occurs this bit controls the severity of the reported error If this bit is set the event is rep...

Page 136: ...RCES register the corresponding event is not reported to the root complex 7 BADDLLP RW 0x0 Sticky Bad DLLP Mask When this bit is set the corresponding bit in the AERCES register is masked When a bit i...

Page 137: ...ion is enabled 7 ECRCCC RWL 0x1 ECRC Check Capable This bit indicates if the device is capable of checking ECRC 8 ECRCCE RW 0x0 Sticky ECRC Check Enable When set this bit enables ECRC checking 31 9 Re...

Page 138: ...iption 15 0 CAPID RO 0x3 Capability ID The value of 0x3 indicates a device serial num ber capability structure 19 16 CAPVER RO 0x1 Capability Version The value of 0x1 indicates compatibility with vers...

Page 139: ...Count The value of 0x0 indi cates that all VCs are in the upper priority group and are arbi trated based on strict priority VC7 highest VC0 lowest 7 Reserved RO 0x0 Reserved field 9 8 REFCLK RO 0x0 Re...

Page 140: ...it when set updates the VC arbitration logic from the VC Arbitration Table for the VC resource Since the device does not implement a VC arbitration table this field has no functional effect This bit a...

Page 141: ...e port arbitration table from the base address of the Vir tual Channel Capability structure in double quad words 16 bytes Bit Field Field Name Type Default Value Description 7 0 TCVCMAP bit 0 RO bits...

Page 142: ...d only when the port arbitration table is used by the selected arbitration algorithm This bit is set when any entry of the port arbitration table is written by software and remains set until hardware...

Page 143: ...e VC resource In addition this field is only valid when the Port Arbitration Table is used by the selected Port Arbitra tion scheme that is indicated by a set bit in the Port Arbitra tion Capability f...

Page 144: ...me Type Default Value Description 3 0 PHASE0 RW 0x0 Phase 0 This field contains the port ID for the corresponding port arbitration period Selecting an invalid port ID results in the entry being skippe...

Page 145: ...ID for the correspond ing port arbitration period 19 16 PHASE12 RW 0x6 Phase 12 This field contains the port ID for the correspond ing port arbitration period 23 20 PHASE13 RW 0x6 Phase 13 This field...

Page 146: ...iod 7 4 PHASE25 RW 0xC Phase 25 This field contains the port ID for the correspond ing port arbitration period 11 8 PHASE26 RW 0xD Phase 26 This field contains the port ID for the correspond ing port...

Page 147: ...1 This field contains the port ID for the corresponding port arbitration period 11 8 PHASE2 RW 0x1 Phase 2 This field contains the port ID for the corresponding port arbitration period 15 12 PHASE3 R...

Page 148: ...e port ID for the correspond ing port arbitration period 11 8 PHASE18 RW 0x9 Phase 18 This field contains the port ID for the correspond ing port arbitration period 15 12 PHASE19 RW 0x9 Phase 19 This...

Page 149: ...d Name Type Default Value Description 15 0 CAPID RWL 0x0 Capability ID The value of 0x4 indicates a power budgeting capability structure If the power budgeting capability is used then this field shoul...

Page 150: ...it indicates that the power budget for the device is included within the system power budget and that reported power data for this device should be ignored If the power budgeting capability is used t...

Page 151: ...set 6 CCLKUS RO HWINIT Common Clock Upstream This bit reflects the value of the CCLKUS signal sampled during the fundamental reset 7 MSMBSMODE RO HWINIT Master SMBus Slow Mode This bit reflects the va...

Page 152: ...locked 0x1 port1locked Upstream port is locked with port 1 0x2 port2locked Upstream port is locked with port 2 0x3 port3locked Upstream port is locked with port 3 0x4 port4locked Upstream port is lock...

Page 153: ...gis ters and fields of type Read and Write when Unlocked RWL are modified when written to When this bit is cleared all reg isters and fields denoted as RWL become read only While the initial value of...

Page 154: ...ut is inverted in all ports 7 IPXILOCKP RW 0x0 Sticky Invert Polarity of PxILOCKP When this bit is set the polar ity of the PxILOCKP output is inverted in all ports 8 IPXP WRGDN RW 0x0 Sticky Invert P...

Page 155: ...S A value of zero corresponds to no delay The default value corresponds to 200 mS Bit Field Field Name Type Default Value Description 31 0 DATA RW 0x0 Data General purpose register available for softw...

Page 156: ...interface 23 16 Reserved RO 0x0 Reserved field 24 EEPROM DONE RO 0x0 Serial EEPROM Initialization Done When the switch is con figured to operate in a mode in which serial EEPROM initial ization occurs...

Page 157: ...to operate in slow mode i e 100 KHz in the boot configuration and to 0x00531 when it is configured to operate in fast mode i e 400 KHz 16 MSMBIOM RW 0x0 Sticky Master SMBus Ignore Other Masters When t...

Page 158: ...meter is not critical the operating frequency may be increased Bit Field Field Name Type Default Value Description 15 0 ADDR RW 0x0 EEPROM Address This field contains the byte address in the Serial EE...

Page 159: ...set the value for outputs supplied to the I O expander selected by the SEL field correspond to the value written to this field instead of the value supplied by internal logic Bits in this field which...

Page 160: ...Bus transaction com pletes The I O expander is in test mode i e IOEXTM bit set the IOEDATA field is written the corresponding I O expander is selected by the SELECT field in this register and the corr...

Page 161: ...OE5ADDR RWL 0x0 Sticky I O Expander 5 Address This field contains the SMBus address assigned to I O expander 5 on the master SMBus interface 16 Reserved RO 0x0 Reserved field 23 17 IOE6ADDR RWL 0x0 St...

Page 162: ...and PME event notification mecha nisms defined by the PCIe base 1 1 specification are disabled for port 2 and are instead signalled through General Purpose Event GPEN signal assertions GPEN is an alt...

Page 163: ...gnalled through General Purpose Event GPEN signal assertions GPEN is an alternate func tion of GPIO 9 10 P10GPEE RW 0x0 Sticky Port 10 General Purpose Event Enable When this bit is set the hot plug IN...

Page 164: ...nabled in the GPECTL register GPEN is an alternate function of GPIO 5 and GPIO 5 is asserted only if enabled to operate as an alternate function 2 P2GPES RO 0x0 Port 2 General Purpose Event Status Whe...

Page 165: ...sponding port is signalling a general purpose event by asserting the GPEN signal This bit is never set if the corre sponding general purpose event is not enabled in the GPECTL register GPEN is an alte...

Page 166: ...IO 5 and GPIO 5 is asserted only if enabled to operate as an alternate function 15 P15GPES RO 0x0 Port 15 General Purpose Event Status When this bit is set the corresponding port is signalling a gener...

Page 167: ...PFSTS The USPSEL signal is a GPIO alternate function This field has no effect on system operation when the an upstream port failover switch mode has not been selected during a fundamental reset 2 TIMF...

Page 168: ...core from this port i e those received on the ingress port or generated by the port whose TLP header length field i e bits seven through zero of byte zero of the TLP header match the value in the Err...

Page 169: ...ame Type Default Value Description 7 0 EEPEC RCW 0x0 Sticky End to End Parity Error Count This field is incremented each time an end to end parity error is detected at the port until it saturates at i...

Page 170: ...rates an ERR_COR mes sage to the root 0x2 nonfatal The port generates an ERR_NONFATAL message to the root 0x3 fatal The port generates an ERR_FATAL message to the root 5 4 CPTLPTO RW 0x0 Sticky Comple...

Page 171: ...e a TLP is discarded from the port s IFB non posted queue because it is more than 50 ms old This counter saturates at its maximum value Reading this field causes it to be cleared 23 16 CTLPTOC RCW 0x0...

Page 172: ...IDT Configuration Registers PES34H16 User Manual 9 80 October 30 2008 Notes...

Page 173: ...6 Test Access Point The system logic utilizes a 16 state TAP controller a six bit instruction register and five dedicated pins to perform a variety of functions The primary use of the JTAG TAP Control...

Page 174: ...T active low Asynchronous reset for JTAG TAP controller internal pull up JTAG_TCK Input JTAG Clock Test logic clock JTAG_TMS and JTAG_TDI are sampled on the rising edge JTAG_TDO is output on the falli...

Page 175: ...E1TN 3 0 O O C PE1TP 3 0 PE2RN 3 0 I O PE2RP 3 0 I O PE2TN 3 0 O O C PE2TP 3 0 PE3RN 3 0 I O PE3RP 3 0 I O PE3TN 3 0 O O C PE3TP 3 0 PE4RN 3 0 I O PE4RP 3 0 I O PE4TN 3 0 O O C PE4TP 3 0 PE5RN 3 0 I O...

Page 176: ...0 I O PE12TN 0 O O C PE12TP 0 PE13RN 0 I O PE13RP 0 I O PE13TN 0 O O C PE13TP 0 PE14RN 0 I O PE14RP 0 I O PE14TN 0 O O C PE14TP 0 PE15RN 0 I O PE15RP 0 I O PE15TN 0 O O C PE15TP 0 PEREFCLKN 3 0 I PER...

Page 177: ...s currently held in the boundary scan register s output latches is immediately transferred to the corresponding outputs or output enables Therefore the SAMPLE PRELOAD instruction must first be used to...

Page 178: ...utput cells is shown in Figure 10 4 Figure 10 4 Diagram of Output Cell The output enable cells are also output cells The simplified logic is shown in Figure 10 5 Input Pin shift_dr From previous cell...

Page 179: ...ster allows an instruction to be shifted serially into the device at the rising edge of JTAG_TCK The instruction is then used to select the test to be performed or the test register to be accessed or...

Page 180: ...te rapid testing of a given device all other devices are put into BYPASS mode Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec tions Data is t...

Page 181: ...the device contains a Device ID register the first bit is a 1 or if the device only contains a BYPASS register the first bit is 0 However even if the device contains a Device ID register it must also...

Page 182: ...to either drive a zero on the JTAG_TCK pin when it is not being used or to use an external pull down resistor In order to guarantee that the JTAG does not interfere with normal system operation the T...

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