IDT 89HPES34H16, User Manual, Page: 46 / 182

IDT Clocking, Reset, and Initialization Clock Operation
PES34H16 User Manual 3 - 6 October 30, 2008
Notes
The PCIe base specification indicates that normal operation should begin within 1.0 second after a
fundamental reset of a device. The reset sequence above guarantees that normal operation will begin
within this period as long as the serial EEPROM initialization process completes within 200 ms. Under
normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a Master
SMBus operating frequency of 100 KHz.
Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.
A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch Control
(SWCTL) register always results in the PES34H16 returning a completion to the requester before the warm
reset process begins.
The PES34H16 provides a reset output signal for each downstream port implemented as a GPIO alter-
nate function. When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the
downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they
are used as reset outputs.
The operation of a fundamental reset with serial EEPROM initialization (i.e., SWMODE[3:0] = 0x1) is
illustrated in Figure 3.5.
Figure 3.5 Fundamental Reset in Transparent Mode with Serial EEPROM Initialization
Hot Reset
A hot reset may be initiated by any of the following conditions:
– Reception of TS1 ordered-sets on the upstream port indicating a hot reset.
– Data link layer of the upstream port transitions to the DL_Down state.
– Writing a one to the Hot Reset (HRST) bit in the System Control (SWCTL) register.
REFCLK
Vdd
PERSTN
SerDes
Master SMBus
Slave SMBus
Tpvperl
PLL Reset and Lock CDR Reset & Lock Ready for Normal Operation
Ready for Normal Operation
Ready Idle Serial EEPROM Initialization
11
μ
s
20ms max.
50
μ
s max.
Link Training
RSTHALT bit cleared
in SWCTL
Stacks in Quasi Reset State
Notes:
1) Reference Clock (REFCLK) not shown to scale.
2) The PES34H16 requires a minimum time for Tperst-clk of 1µs. The PES34H16 requires a minimum time for Tpvperl of 1ms.
3) In a system, the values of Tpvperl and Tperst-clk depend on the mechanical form factor in which the PES34H16 is used. For example,
the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µ s and Tpvperl=100ms.