IDT 89HPES34H16, User Manual, Page: 33 / 182

IDT PES34H16 Device Overview
PES34H16 User Manual 1 - 15 October 30, 2008
Notes
Port Configuration
The PES34H16 contains up to 6 x4 ports and ten x1 ports labeled 0 through 15. Port 0 is always the
upstream port and ports 1 through 15 are always downstream ports. An even port n and its odd counterpart,
port n+1, may be merged into a single x8 port (ports 0 through 3 only). When this occurs, port n is said to be
a merged port. When an even port n and its odd counterpart, port n+1, operate independently, then ports n
and n+1 are said to be unmerged.
The PES34H16 supports port merging in a static manner during a fundamental reset. If the Port x and y
Merge (PxyMERGEN) signal is asserted, then the two x4 ports x and y are merged into a single x8 merged
port called port x. When ports x and y are merged, the switch port, the PCI-to-PCI bridge, and all associated
resources associated with port y are disabled and the following modifications are made to the default
PES34H16 configuration.
– All of the output signals associated with port y remain in a negated state (e.g., hot-plug outputs,
link status signals, port reset output, etc.)
– All input signals associated with port y are ignored by the PES34H16 and have no effect on its
operation.
– Configuration read or write transactions to device y on the PES34H16’s virtual PCI bus are treated
by the upstream port (port 0) as unsupported requests (i.e., the device no longer exists).
• This renders the registers in port y’s configuration space inaccessible to the root.
– All registers associated with port y become inaccessible via the SMBus. Reading or writing an
inaccessible register has an undefined effect.
• Reading a port y register returns an undefined value and writing a port y register has an unde-
fined effect.
– All of the SerDes lanes associated with port y become part of port x and are managed by port x as
native SerDes lanes (i.e., port x operates as though it were a x8 port).
– The initial value of the MAXLNKWDTH field in port x’s PCIELCAP register defaults to x8 mode.
Figures 1.3 and 1.4 illustrate two possible PES34H16 configurations. In Figure 1.3, all of the ports are
unmerged. In this configuration, the PES34H16 operates as a 16-port switch with all ports 0 through 5
having a x4 width, and ports 6 through 15 having a x1 width. In Figure 1.4, even ports 0, 2, and 4 are
merged with their corresponding odd ports, and ports 6 through 15 remain x1 width. In this configuration,
the PES34H16 operates as a 13-port.
Figure 1.3 All Ports Unmerged Configuration
PES34H16
PCI to PCI
Bridge
PCI to PCI
Bridge
Dev. 1
PCI to PCI
Bridge
Dev. 5
PCI to PCI
Bridge
Dev. 6
PCI to PCI
Bridge
Dev. 15
Dev. 0
Port 0
Virtual PCI Bus
x4
Port 1
x4
Port 5
x4
Port 6
x1
Port 15
x1
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