IDT 89HPES16T4G2, Preliminary User'S Manual

Page: 137 / 149

IDT Configuration Registers
PES16T4G2 User Manual 8 - 59 January 28, 2013
Notes
IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434)
IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438)
GPECTL - General Purpose Event Control (0x450)
Bit
Field
Field
Name
Type Default
Value
Description
0 Reserved RO 0x0 Reserved field.
7:1 IOE0ADDR RWL 0x0
Sticky
I/O Expander 0 Address. This field contains the SMBus address
assigned to I/O expander 0 on the master SMBus interface.
16:8 Reserved RO 0x0 Reserved field.
23:17 IOE2ADDR RWL 0x0
Sticky
I/O Expander 2 Address. This field contains the SMBus address
assigned to I/O expander 2 on the master SMBus interface.
31:24 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
0 Reserved RO 0x0 Reserved field.
7:1 IOE4ADDR RWL 0x0
Sticky
I/O Expander 4 Address. This field contains the SMBus address
assigned to I/O expander 4 on the master SMBus interface.
31:8 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
0 IGPE RW 0x0
Sticky
Invert General Purpose Event Enable Signal Polarity. When
this bit is set, the polarity of all General Purpose Event (GPEN) sig-
nals is inverted.
0x0 -(normal) GPEN signals are active low
0x1 -(invert) GPEN signals are active high
1 Reserved RO 0x0 Reserved field.
2 P2GPEE RW 0x0
Sticky
Port 2 General Purpose Event Enable. When this bit is set, the
hot-plug INTx, MSI and PME event notification mechanisms
defined by the PCIe base 2.0 specification are disabled for port 2
and are instead signalled through General Purpose Event (GPEN)
signal assertions. GPEN is an alternate function of GPIO[7].
3 Reserved RO 0x0 Reserved field.
4 P4GPEE RW 0x0
Sticky
Port 4 General Purpose Event Enable. When this bit is set, the
hot-plug INTx, MSI and PME event notification mechanisms
defined by the PCIe base 2.0 specification are disabled for port 4
and are instead signalled through General Purpose Event (GPEN)
signal assertions. GPEN is an alternate function of GPIO[7].
5 Reserved RO 0x0 Reserved field.