IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Clocking, Reset and Initialization
PES12T3G2 User Manual 2 - 6 January 28, 2013
Notes
• If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link
State 0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using
the current link parameters.
• If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM
is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in
the SMBUSSTS register.
• When serial EEPROM initialization completes or when an error is detected, the DONE bit in the
SMBUSSTS register is set.
7. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state
except the master and slave SMBuses. The RSTHALT bit is only set if serial EEPROM initialization
is enabled in step 6.
8. Normal device operation begins.
The operation of the slave SMBus interface is unaffected by a hot reset. Using the slave SMBus to
access a register that is reset by a hot reset causes zero to be returned on a read and written data to be
ignored on writes.
A hot reset initiated by the writing of a one to the Hot Reset (HRST) bit in the Switch Control (SWCTL)
register always results in the PES12T3G2 returning a completion to the requester before the hot reset
process begins. Additionally, the upstream link is fully retrained (i.e., the upstream LTSSM transitions to the
Detect state).
Upstream Secondary Bus Reset
An Upstream Secondary Bus Reset may be initiated by the following condition:
– A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port’s (i.e., port 0)
Bridge Control Register (BCTL).
When an Upstream Secondary Bus Reset occurs, the following sequence is executed.
1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with
the hot reset bit set.
2. All registers fields in all registers associated with downstream ports, except those denoted as “sticky”
or Read and Write when Unlocked (i.e, RWL), are reset to their initial value. The value of fields
denoted as “sticky” or RWL is unaffected by an Upstream Secondary Bus Reset.
3. All TLPs received from downstream ports and queued in the PES12T3G2 are discarded.
4. Logic in the stack, application layer and switch core associated with the downstream ports are grace-
fully reset.
5. Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port’s Bridge
Control Register (BCTL).
6. Normal downstream port operation begins.
The operation of the upstream port is unaffected by a secondary bus reset. The link remains up and
Type 0 configuration read and write transactions that target the upstream port complete normally.
During an Upstream Secondary Bus Reset, all TLPs destined to the secondary side of the upstream
port’s PCI-to-PCI bridge are treated in an undefined manner. The user should ensure no TLPs are sent to
the secondary side of the upstream port’s PCI-to-PCI bridge until the SRESET bit in the BCTL register is
cleared.
The operation of the slave SMBus interface is unaffected by an Upstream Secondary Bus Reset. Using
the slave SMBus to access a register that is reset by an Upstream Secondary Bus Reset causes the
register’s default value to be returned on a read and written data to be ignored on writes.
Downstream Secondary Bus Reset
A Downstream Secondary Bus Reset may be initiated by the following condition:
– A one is written to the Secondary Bus Reset (SRESET) bit in a downstream port’s Bridge Control
Register (BCTL).