IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT PES12T3G2 Device Overview
PES12T3G2 User Manual 1 - 4 January 28, 2013
Notes
System Identification
Vendor ID
All vendor ID fields in the device are hardwired to 0x111D which corresponds to Integrated Device Tech-
nology, Inc.
Device ID
The PES12T3G2 device ID is shown in Table 1.1.
Revision ID
The PES12T3G2 revision ID is shown in Table 1.2.
JTAG ID
The JTAG ID is:
– Version: Same value as Revision ID. See Table 1.2
– Part number: Same value as base Device ID. See Table 1.1.
– Manufacturer ID: 0x33
– LSB: 0x1
Pin Description
The following tables list the functions of the pins provided on the PES12T3G2. Some of the functions
listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals
ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals
(including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic
one (high) level.
Note: In the PES12T3G2, the two downstream ports are labeled port 2 and port 4.
PCIe Device Device ID
0x1 0x8061
Table 1.1 PES12T3G2 Device ID
Revision ID Description
0x0 Corresponds to ZA silicon
0x1 Corresponds to ZB silicon
Table 1.2 PES12T3G2 Revision ID
Signal Type Name/Description
PE0RP[3:0]
PE0RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PE0TP[3:0]
PE0TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PE2RP[3:0]
PE2RN[3:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
Table 1.3 PCI Express Interface Pins (Part 1 of 2)