IDT 89HPES12N3, User Manual

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IDT Transparent Mode Operation Upstream Port A Configuration Space Registers
PES12N3 User Manual 9 - 8 June 7, 2006
Notes
Upstream Port A Configuration Space Registers
All configuration space locations not listed in Table 9.6 return a value of zero when read. Writes to these
locations are ignored and have no side-effects.
Port A configuration space registers may be read and written via the slave SMBus interface and initial-
ized from the serial EEPROM using the CSR system address formed by adding the base address 0x0000
to the PCI configuration space offset address.
Note: In pdf format, clicking on a register name in the Register Definition column creates a jump
to the appropriate register. To return to the starting place in this table, click on the same register
name (in blue) in the register section.
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
0x000 Word PA_VID VID - Vendor Identification (0x000) on page 9-17
0x002 Word PA_DID DID - Device Identification (0x002) on page 9-17
0x004 Word PA_PCICMD PCICMD - PCI Command (0x004) on page 9-17
0x006 Word PA_PCISTS PCISTS - PCI Status (0x006) on page 9-18
0x008 Byte PA_RID RID - Revision Identification (0x008) on page 9-19
0x009 3 Bytes PA_CCODE CCODE - Class Code (0x009) on page 9-19
0x00C Byte PA_CLS CLS - Cache Line Size (0x00C) on page 9-20
0x00D Byte PA_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 9-20
0x00E Byte PA_HDR HDR - Header Type Register (0x00E) on page 9-20
0x00F Byte PA_BIST BIST - Built-in Self Test (0x00F) on page 9-20
0x010 DWord PA_BAR0 BAR0 - Base Address Register 0 (0x010) on page 9-20
0x014 DWord PA_BAR1 BAR1 - Base Address Register 1 (0x014) on page 9-20
0x018 Byte PA_PBUSN PBUSN - Primary Bus Number (0x018) on page 9-21
0x019 Byte PA_SBUSN SBUSN - Secondary Bus Number (0x019) on page 9-21
0x01A Byte PA_SUBUSN SUBUSN - Subordinate Bus Number (0x01A) on page 9-21
0x01B Byte PA_SLTIMER SLTIMER - Secondary Latency Timer (0x01B) on page 9-21
0x01C Byte PA_IOBASE IOBASE - I/O Base (0x01C) on page 9-21
0x01D Byte PA_IOLIMIT IOLIMIT - I/O Limit (0x01D) on page 9-22
0x01E Word PA_SECSTS SECSTS - Secondary Status (0x01E) on page 9-22
0x020 Word PA_MBASE MBASE - Memory Base (0x020) on page 9-23
0x022 Word PA_MLIMIT MLIMIT - Memory Limit (0x022) on page 9-23
0x024 Word PA_PMBASE PMBASE - Prefetchable Memory Base (0x024) on page 9-23
0x026 Word PA_PMLIMIT PMLIMIT - Prefetchable Memory Limit (0x026) on page 9-24
0x028 DWord PA_PMBASEU PMBASEU - Prefetchable Memory Base Upper (0x028) on page
9-24
0x02C DWord PA_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper (0x02C) on page
9-24
0x030 Word PA_IOBASEU IOBASEU - I/O Base Upper (0x030) on page 9-24
Table 9.6 Upstream Port A Configuration Space Registers (Part 1 of 3)