IDT 89HPES12N3, User Manual

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Notes
PES12N3 User Manual 8 - 1 June 7, 2006
Chapter 8
General Purpose I/O
Introduction
The PES12N3 has eight General Purpose I/O (GPIO) pins that may be individually configured as:
general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the
General Purpose I/O Control and Status (GPIOCS) register located in upstream port A’s PCI configuration
space (see Table 8.1).
GPIO Registers
As shown in Table 8.2, GPIO pins [5:0] are shared with other on-chip functions. The GPIO Function
(GPIOFUNC) field in the GPIOCS register controls whether a GPIO bit operates as a general purpose I/O
or as the specified alternate function.
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 GPIOFUNC RW 0x0 GPIO Function. Each bit in this field controls the corre-
sponding GPIO pin. When set to a one, the corresponding
GPIO pin operates as the alternate function as defined in
Table 8.2. When a bit is cleared to a zero, the correspond-
ing GPIO pin operates as a general purpose I/O pin.
15:8 GPIOCFG RW 0x0 GPIO Configuration. Each bit in this field controls the cor-
responding GPIO pin. When a bit is configured as a gen-
eral purpose I/O pin and the corresponding bit in this field
is set, then the pin is configured as a GPIO output. When a
bit is configured as a general purpose I/O pin and the cor-
responding bit in this field is zero, then the pin is config-
ured as an input. When the pin is configured as an
alternate function, the behavior of the pin is defined by the
alternate function.
23:16 GPIOD RW HWINIT GPIO Data. Each bit in this field controls the correspond-
ing GPIO pin. Reading this field returns the current value
of each GPIO pin regardless of GPIO pin mode (i.e., alter-
nate function or GPIO pin). Writing a value to this field
causes the corresponding pins which are configured as
GPIO outputs to change state to the value written.
31:24 Reserved RO 0x0 Reserved field.
Table 8.1 General Purpose IO Registers