IDT 89HPES12N3, User Manual

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IDT PES12N3 Device Overview System Identification
PES12N3 User Manual 1 - 4 June 7, 2006
Notes
– Supports ECRC passed through
– Supports PCI Express Native Hot-Plug
• Compatible with Hot-Plug I/O expanders used on PC motherboards
– Supports Hot-Swap
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Power Management
– Supports PCI Express Power Management Interface specification, Revision 1.1 (PCI-PM)
– Unused SerDes are disabled
– Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI)
supporting active link state
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Testability and Debug Features
– Supports IEEE 1149.6 JTAG
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
–
Provides statistics and performance counters
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Two SMBus Interfaces
– Slave interface provides full access to all software-visible registers by an external SMBus master
– Master interface provides connection for an optional serial EEPROM used for initialization
– Master interface is also used by an external Hot-Plug
I/O expander
– Master and slave interfaces may be tied together so the PES12N3 can act as both master and
slave
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8 General Purpose Input/Output pins
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Packaged in 19x19mm 324 ball BCG with 1mm ball spacing
System Identification
Vendor ID
All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech-
nology, Inc.
Device ID
The device IDs for the PES12N3 are shown in Table 1.1.
PCI Device
Offset
Device ID
Transparent bridge associ-
ated with Ports A, B, and C 0x8018
Table 1.1 PES12N3 Offset Device IDs