IDT 89EBPES24T3G2, Manual

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IDT Installation of the EB24T3G2 Eval Board
EB24T3G2 Eval Board Manual 2 - 3 January 21, 2008
Notes
Power-up Sequence
During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDIO at all times. There
are no other power-up sequence requirements for the various operating supply voltages.
Reset
The PES24T3G2 supports two types of reset mechanisms as described in the PCI Express specifica-
tion:
– Fundamental Reset: This is a system-generated reset that propagates along the PCI Express
tree through a single side-band signal PERST# which is connected to the Root Complex, the
PES24T3G2, and the endpoints.
– Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to
another. Hot Reset may be initiated by software. This is further discussed in the 89HPES24T3G2
User Manual. The EB24T3G2 evaluation board provides seamless support for Hot Reset.
Fundamental Reset
There are two types of Fundamental Resets which may occur on the EB24T3G2 evaluation board:
– Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI
Express Reset (PERSTN) input pin of the PES24T3G2.
– Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be
initiated by two methods:
• Pressing a push-button switch (S1) located on EB24T3G2 board
• The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB24T3G2. Note that one can bypass the onboard
voltage monitor (TLC7733D) by moving the shunt from pin 1-2 to pin 2-3 (default) on W4.
Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES24T3G2 while power is on.
Downstream Reset
The PES24T3G2 provides a a choice of either a software-controlled reset for each downstream port
through GPIO pins or a fundamental reset through PERST#. Selection is made by jumpers described in
Table 2.4.
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 2.5 is sampled by the PES24T3G2
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S7 and S8 as defined in Table 2.6.
Port # Jumper Selection
2 W19 [1-2] Software controlled reset through GPIO0
[2-3] Fundamental reset PERST# (default)
4 W18 [1-2] Software controlled reset through GPIO1
[2-3] Fundamental reset PERST# (default)
Table 2.4 Downstream Reset Selection