IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual
2 - 4
November 13, 2007
Notes
Fundamental Reset
There are two types of Fundamental Resets which may occur on the EB16NT2 evaluation board:
–
Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI
Express Reset (PERSTN) input pin of the PES16NT2.
–
Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be
initiated by two methods:
•
Pressing a push-button switch (S1) located on EB16NT2 board
•
The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB16NT2. Note that one can bypass the onboard
voltage monitor (TLC7733D) by moving the resistor from pin 1-2 to pin 2-3 on W27.
Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES16NT2 while power is on.
An external side fundamental reset is initiated when the switch is configured to operate in non-trans-
parent mode and the PCI Express Non-Transparent Bridge Reset (PENTBRST#) signal is asserted. This
results in the resetting of the transaction, data link, and PHY layers associated with the external side of the
non-transparent bridge. The initialization of all registers associated with the external side of the non-trans-
parent bridge are set to their initial values except those with a read and write when unlocked attribute and
those associated with the non-transparent bridge configuration capability structure.
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 2.4 is sampled by the PES16NT2
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S5 and S6 as defined in Table 2.5.
Signal
Description
CCLKDS
Common Clock Downstream.
The assertion of this pin indicates that all downstream
ports are using the same clock source as that provided to downstream devices. This pin is
used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers
for downstream ports. The value may be overridden by modifying the SCLK bit in the down-
stream port’s PCIELSTS register.
Default: 0x1
CCLKUS
Common Clock Upstream.
The assertion of this pin indicates that the upstream port is
using the same clock source as the upstream device. This pin is used as the initial value of
the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value
may be overridden by modifying the SCLK bit in the P0_PCIELSTS register.
Default: 0x1
MSMBSMODE
Master SMBus Slow Mode.
The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 kHz.
Default: 0x0
RSTHALT
Reset Halt.
When this signal is asserted during a PCI Express fundamental reset, the
PES16NT2 executes the reset procedure and remains in a reset state with the Master and
Slave SMBuses active. This allows software to read and write registers internal to the
device before normal device operation begins. The device exits the reset state when the
RSTHALT bit is cleared in the P0_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the P0_SWCTL register.
Default: 0x0
Table 2.4 Boot Configuration Vector Signals (Part 1 of 2)
Summary of Contents for 89EBPES16NT2
Page 4: ...IDT Table of Contents EB16NT2 Eval Board Manual ii November 13 2007 Notes...
Page 6: ...IDT List of Tables EB16NT2 Eval Board Manual iv November 13 2007 Notes...
Page 8: ...IDT List of Figures EB16NT2 Eval Board Manual vi November 13 2007 Notes...
Page 26: ...IDT Software for the EB16NT2 Eval Board EB16NT2 Eval Board Manual 3 2 November 13 2007 Notes...
Page 27: ...Notes EB16NT2 Eval Board Manual 4 1 November 13 2007 Chapter 4 Schematics Schematics...
