IDT 89EBPES16NT2, Manual

Page: 15 / 36

IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 5 November 13, 2007
Notes
SMBus Interfaces
The System Management Bus (SMBus) is a two-wire interface through which various system compo-
nent chips can communicate. It is based on the principles of operation of I
2
C. Implementation of the SMBus
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consists of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins.
SWMODE[2:0] Switch Mode. These configuration pins determine the PES16NT2 switch operating mode.
Default: 0x1
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM-based initialization
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode serial EEPROM initialization
0x7 - 0xF Reserved
Default: 0x0
REFCLKM PCI Express Reference Clock Mode Select . This signal selects the frequency of the ref-
erence clock input. Default: 0x0
0x0 - 100 MHz
0x1 - 125 MHz
MSMBADDR[2:0] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM
from which configuration information is loaded. Default: 0x0
Signal Description Default
S6[1] CCLKDS OFF
S6[2] CCLKUS OFF
S6[3] SWMODE[3] ON
S6[4] SWMODE[2] ON
S6[5] SWMODE[1] ON
S6[6] SWMODE[0] ON
S6[7] Not Used ON
S6[8] Not Used ON
S5[1] MSMBADDR[4] ON
S5[2] MSMBADDR[3] ON
S5[3] MSMBADDR[2] ON
S5[4] MSMBADDR[1] ON
S5[5] REFCLKM ON
S6[6] RSTHALT# ON
S6[7] MSMBSMODE ON
S5[8] Not Used ON
Table 2.5 Boot Configuration Vector Switches S7 & S8 (ON=0, OFF=1)
Signal Description
Table 2.4 Boot Configuration Vector Signals (Part 2 of 2)