10
REVISION C 09/29/14
82P33731/33831 EVALUATION BOARD
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G.8273.2: to configure the DPLL for T-BC (Telecom Boundary Clock), which occurs when a IEEE-1588 stack is
directly controlling the DCO with phase offsets. It also puts the DPLL in combo mode to synchronize to the other PLL
running G.8262-Option 1 profile
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Lock to 1Hz: to configure the DPLL for GPS application and locking to 1PPS only
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Wideband: to configure the DPLL to operate in line card mode or lock to a 10MHz + 1PPS from GPS
Figure 9. Frequency Profiles for DPLL1
Click “Configure” button to open up configuration window for respective DPLL for additional or customized configuration.
There are pull-down items for each configuration parameter. For example, in “Operation Mode” section, you can select:
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Automatic, or Free-up to force Lock or Free-run;
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Different base frequencies can be selected from pull-down items in Selector A or Select B;
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Input reference can be set manually set to a particular input, or set it in “Automatic” mode, in which case a input
reference is selected based on priority among multiple input references;
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Feedback can be “Internal feedback mode” or use one of the input references as an “external feedback mode”. When
in external feedback mode, a clock source must be supplied to the input chosen at the same frequency as the input
to the DPLL (typically, it's 8kHz).
