Technical Description 3-3
Register Description
Note:
Interrupt source is Base+0 bit D0. When selecting the Interrupt Mode,
always disable interrupts prior to changing or setting states. This will
help prevent inadvertent or un-expected interrupts from occurring.
When using the high and low level interrupts, a change in state of the
input must occur before the interrupt can be cleared.
The device
providing the input to Base +0, bit D0 must do this.
PAD0-7
= Port A (Base+0)
PBD0-7
= Port B (Base+1)
IRC0-1= Interrupt Mode select (Base+5)
IRC1
IRC0
0
0
low level
0
1
high level
1
0
falling edge
1
1
rising edge
IRQEN = enable interrupts (Base+5)
0 = disabled
1 = enabled (disabled after reset or power up).
IRQST = interrupt status (Base+5)
1 = interrupt pending (reading the bit clears interrupt).
Address
Mode
D7
D6
D5
D4
D3
D2
D1
D0
Base+0
RD/WR
PAD7
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD0
Base+1
RD/WR
PBD7
PBD6
PBD5
PBD4
PBD3
PBD2
PBD1
PBD0
Base+2
RD/WR
{0}
{0}
{0}
{0}
{0}
{0}
{0}
{0}
Base+3
RD/WR
{0}
{0}
{0}
{0}
{0}
{0}
{0}
{0}
Base+4
RD/WR
{0}
{0}
{0}
{0}
{0}
{0}
{0}
{0}
Base+5
RD/WR
IRQEN
IRQST
{0}
{0}
{0}
{0}
IRC1
IRC0
Base+6
RD Only
{0}
{0}
{0}
{0}
{0}
{0}
{0}
{0}
Base+7
RD Only
{0}
{0}
{0}
{0}
{0}
{0}
{0}
{0}
Summary of Contents for PCI-16ISO
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