ICS Advent WDT-1002, Product Manual

Page: 22 / 34

Manual Number: 00650-009-28 Page 5-2
WDT1000-P Manual
RL1 and RL0: These bits control reading and loading of the Counter/Timer selected by SC1 and
SC0. RL1 is the most significant bit and code assignment is:
00 = Counter Latching
01 = Read/Load Least significant Byte Only
10 = Read/Load Most Significant Byte Only
11 = Read/Load Least, Then Most Significant Byte
BCD: This bit commands counting modulus; 0= binary, 1= BCD.
M2, M1, and M0: These bits control the operating mode of the Counter/Timer selected by SC1 and
SC0. Bit assignments and mode commanded are as follows:
(table5-3.tbl)
0 0 0 0RGH
0RGH3XOVHRQWHUPLQDOFRXQW
0RGH 5HWULJJHUDEOH RQHVKRW
[ 0RGH 5DWH JHQHUDWRU
[ 0RGH6TXDUH:DYHJHQHUDWRU
0RGH6RIWZDUHWULJJHUHGVWUREH
0RGH+DUGZDUHWULJJHUHGVWUREH
The 8253 modes of operation are described in the following paragraphs to familiarize you with the
versatility and power of this device. The following definitions apply for use in describing operation
of the 8253 :
Clock: A positive pulse into the counter’s clock input.
Trigger: A rising edge input to the counter’s gate input.
Counter Loading: Programming of a binary count into the counter.
Mode 0: Pulse on Terminal Count
After the counter is loaded, the output is set low and will remain low until the counter decrements to
zero. The output then goes high and remains high until a new count is loaded into the counter. A
trigger enables the counter to start decrementing. This mode is commonly used for event counting
with Counter #0.