ICP DAS USA PIO-D144 Series User Manual Download Page 27

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PIO-D144 User’s Manual

Version: 2.1 Date: 1999/10 Page 27

3.3 The I/O Address Map

The I/O address of PIO/PISO series card is automatically assigned by

the main board ROM BIOS. The I/O address can also be re-assigned by user.

It is strongly recommended not to change the I/O address by user. The

Plug&Play BIOS will assign proper I/O address to each PIO/PISO series

card very well. The I/O address of PIO-D144 are given as follows:

Address

Read

Write

WBase+0

RESET\ control register

Same

WBase+2

Aux control register

Same

WBase+3

Aux data register

Same

WBase+5

INT mask control register

Same

WBase+7

Aux pin status register

Same

WBase+0x2a INT polarity control register

Same

WBase+0xc0 Read 8-bit data from D/I port Write 8-bit data to D/O port

WBase+0xc4 Reserved

Select the active I/O port

WBase+0xc8 Reserved

I/O Port 0-5 direction control

WBase+0xcc Reserved

I/O Port 6-11 direction control

WBase+0xd0 Reserved

I/O Port 12-17 direction control

Note. Refer to Sec. 3.1 for more information about wBase.

3.3.1 RESET\ Control Register

(Read/Write): wBase+0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET\

Note. Refer to Sec. 3.1 for more information about wBase.

When the PC is first power-on, the RESET\ signal is in Low-state. This will disable

all D/I/O operations. The user has to set the RESET\ signal to High-state before any

D/I/O command.

outp(wBase,1);

/* RESET\=High

all D/I/O are enable now */

outp(wBase,0);

/* RESET\=Low

all D/I/O are disable now */

ГК

Атлант

Инжиниринг

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официальный

представитель

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СНГ

+7(495)109-02-08 [email protected] www.bbrc.ru

Summary of Contents for PIO-D144 Series

Page 1: ...ange this manual at any time without notice The information furnished by ICP DAS is believed to be accurate and reliable However no responsibility is assumed by ICP DAS for its use nor for any infringements of patents or other rights of third parties resulting from its use Copyright Copyright 1999 by ICP DAS All rights are reserved Trademark The names used for identification only maybe registered ...

Page 2: ...DRESS MAP 27 3 3 1 RESET Control Register 27 3 3 2 AUX Control Register 28 3 3 3 AUX data Register 28 3 3 4 INT Mask Control Register 28 3 3 5 Aux Status Register 29 3 3 6 Interrupt Polarity Control Register 29 3 3 7 Read Write 8 bit data Register 30 3 3 8 Active I O Port Control Register 30 3 3 9 I O Selection Control Register 31 4 DEMO PROGRAM 32 4 1 PIO D144 H 33 4 2 DEMO1 USE D O OF CN1 34 4 3...

Page 3: ...independently Each board 6 connector 6 3 port 6 3 8 bit 144 bit 4 interrupt sources PC0 PC1 PC2 PC3 All signals are TTL compatible Operating Temperature 0 C to 60 C Storage Temperature 20 C to 80 C Humility 0 to 90 non condensing Dimension 180mm X 105mm Power Consumption 5V 1100mA 1 2 Product Check List In addition to this manual the package includes the following items PIO D144 card Demo program ...

Page 4: ...S PIO D144 CN1 DB 37 PIN CN1_PA CN1_PC CN1_PB CN3 50 PIN CN3_PA CN3_PC CN3_PB CN6 50 PIN CN6_PA CN6_PC CN6_PB CN4 50 PIN CN4_PA CN4_PC CN4_PB CN5 50 PIN CN5_PA CN5_PC CN5_PB CN2 50 PIN CN2_PA CN2_PC CN2_PB ГК Атлант Инжиниринг официальный представитель в РФ и СНГ 7 495 109 02 08 sales bbrc ru www bbrc ru ...

Page 5: ... disable The enable disable of D I O is controlled by the RESET signal Refer to Sec 3 3 1 for more information about RESET signal The power on states are given as following All D I O operations are disable All eighteen D I O ports are configured as D I port All D O latch register are undefined refer to Sec 2 4 The user has to perform some initialization before using these D I O The recommended ste...

Page 6: ...If D I O is configured as D O port D I read back of D O If D I O is configured as D I port send to D O will change the D O latch register only The D I external input signal will not change disable input Latch Clock input D O latch CKT RESET Sec 3 3 1 Data Sec 3 3 7 I O select Sec 3 3 9 D I O disable Buffer input Clock input D I buffer CKT Data Sec 3 3 7 ГК Атлант Инжиниринг официальный представите...

Page 7: ...nterrupt service routine does not have to identify the interrupt source Refer to DEMO3 C DEMO4 C If there are more than one interrupt source the interrupt service routine has to identify the active signals as following refer to DEMO5 C 1 Read the new status of the interrupt signal source 2 Compare the new status with the old status to identify the active signals 3 If PC0 is active service CN1_PC0 ...

Page 8: ...te low change to high now now_int_state 1 now int_signal is High application codes are given here _outpd wBase 0x2a 1 select the inverted signal else old state high change to low now now_int_state 0 now int_signal is Low application codes are given here _outpd wBase 0x2a 0 select the non inverted signal if wIrq 8 outp A2_8259 0x20 EOI outp A1_8259 0x20 EOI Initial Low ГК Атлант Инжиниринг официаль...

Page 9: ...t_state 0 old state low change to high now now_int_state 1 now int_signal is High application codes are given here _outpd wBase 0x2a 1 select the inverted signal else old state high change to low now now_int_state 0 now int_signal is Low application codes are given here _outpd wBase 0x2a 0 select the non inverted signal if wIrq 8 outp A2_8259 0x20 EOI outp A1_8259 0x20 EOI ГК Атлант Инжиниринг офи...

Page 10: ...hen the interrupt is active the user program has to identify the active signals These signals maybe active at the same time So the interrupt service routine has to service all active signals at the same time CN1_PC1 CN1_PC0 CN1_PC2 CN1_PC3 CN1_PC0 CN1_PC1 are active at the same time CN1_PC2 CN1_PC3 are active at the same time CN1_PC0 CN1_PC1 are return to normal at the same time CN1_PC2 CN1_PC3 ar...

Page 11: ...vert invert 1 4 IF PC1 is active if int_c 0x02 0 cc new_int_state 0x02 if cc 0 CNT_H2 else CNT_L2 invert invert 2 5 IF PC2 is active if int_c 0x04 0 cc new_int_state 0x04 if cc 0 CNT_H3 else CNT_L3 invert invert 4 6 IF PC3 is active if int_c 0x08 0 cc new_int_state 0x08 if cc 0 CNT_H4 else CNT_L4 invert invert 8 now_int_state new_int_state outp wBase 0x2a invert if wIrq 8 outp A2_8259 0x20 outp A1...

Page 12: ...37 with DIN Rail Mounting The DN 50 is designed for 50 pin flat cable header They are designed for easy wire connection Both have Din Rail mounting 2 6 3 DB 8125 The DB 8125 is a general purpose screw terminal board It is designed for easy wire connection There are one DB 37 two 20 pin flat cable header in the DB 8125 DB 8125 for DB 37 or 20 pin flat cable header DN 37 37 PIN cable DB 37 ГК Атлант...

Page 13: ...n header One side of ADP 37 PCI ADP 50 PCI can be connected to a 50 pin header The other side can be mounted on the PC chassis as following ADP 37 PCI 50 pin header to DB 37 extender ADP 50 PCI 50 pin header to 50 pin header extender ГК Атлант Инжиниринг официальный представитель в РФ и СНГ 7 495 109 02 08 sales bbrc ru www bbrc ru ...

Page 14: ...m TTL levels up to 24V or use the DB 24P to sense a wide range of AC signals You can use this board to isolated the computer from large common mode voltage ground loops and transient voltage spike that often occur in industrial environments DB 24P DB 24PD 50 pin flat cable header Yes Yes D sub 37 pin header No Yes Other specifications Same V V PIO D144 DB 24P Opto Isolated PIO D144 50 Pin cable AC...

Page 15: ... associated relay is activated DB 24R DB 24RD 50 pin flat cable header Yes Yes D sub 37 pin header No Yes Other specifications Same DB 24R DB 24RD 24 Relay 120V 0 5A DB 24PR DB 24PRD 24 Power Relay 250V 5A DB 24POR 24 Photo MOS Relay 350V 01 A DB 24SSR 24 SSR 250VAC 4A DB 24C 24 O C 30V 100 mA DB 16P8R 16 Relay 120V 0 5A 8 isolated input DB 24R PIO D144 50 Pin cable Normal Open Normal Close Com No...

Page 16: ...connector just used 16 relays or 50 pin flat cable connector OPTO 22 compatible for DIO 24 series Twenty four enunciator LEDs one for each relay light when their associated relay is activated To avoid overloading your PC s power supply this board needs a 12VDC or 24VDC external power supply DB 24PR PIO D144 50 Pin cable Normal Open COM Note 50 Pin connector OPTO 22 compatible for DIO 24 DIO 48 DIO...

Page 17: ...o Yes DN 37 No No Yes ADP 37 PCI No Yes Yes ADP 50 PCI No Yes No DB 24P No Yes No DB 24PD No Yes Yes DB 16P8R No Yes Yes DB 24R No Yes No DB 24RD No Yes Yes DB 24C Yes Yes Yes DB 24PR Yes Yes No Db 24PRD No Yes Yes DB 24POR Yes Yes Yes DB 24SSR No Yes Yes ГК Атлант Инжиниринг официальный представитель в РФ и СНГ 7 495 109 02 08 sales bbrc ru www bbrc ru ...

Page 18: ... 3 PB7 22 PC7 4 PB6 23 PC6 5 PB5 24 PC5 6 PB4 25 PC4 7 PB3 26 PC3 8 PB2 27 PC2 9 PB1 28 PC1 10 PB0 29 PC0 11 GND 30 PA7 12 N C 31 PA6 13 GND 32 PA5 14 N C 33 PA4 15 GND 34 PA3 16 N C 35 PA2 17 GND 36 PA1 18 VCC 37 PA0 19 GND XXXXXXX This pin not available All signals are TTL compatible ГК Атлант Инжиниринг официальный представитель в РФ и СНГ 7 495 109 02 08 sales bbrc ru www bbrc ru ...

Page 19: ... 8 GND 9 PC3 10 GND 11 PC2 12 GND 13 PC1 14 GND 15 PC0 16 GND 17 PB7 18 GND 19 PB6 20 GND 21 PB5 22 GND 23 PB4 24 GND 25 PB3 26 GND 27 PB2 28 GND 29 PB1 30 GND 31 PB0 32 GND 33 PA7 34 GND 35 PA6 36 GND 37 PA5 38 GND 39 PA4 40 GND 41 PA3 42 GND 43 PA2 44 GND 45 PA1 46 GND 47 PA0 48 GND 49 VCC 50 GND ГК Атлант Инжиниринг официальный представитель в РФ и СНГ 7 495 109 02 08 sales bbrc ru www bbrc ru ...

Page 20: ...Bus wSlotDevice 3 Show_PIO_PISO wSubVendor wSubDevice wSubAux All functions are defined in PIO H Refer to Chapter 4 for more information The important driver information is given as following 1 Resource allocated information wBase BASE address mapping in this PC wIrq IRQ channel number allocated in this PC 2 PIO PISO identification information wSubVendor subVendor ID of this board wSubDevice subDe...

Page 21: ... 03 00 PIO 821 Multi function 80 03 10 PIO DA16 16 D A 80 04 00 PIO DA8 8 D A 80 04 10 PIO DA4 4 D A 80 04 20 PISO C64 64 isolated D O 80 08 00 PISO P64 64 isolated D I 80 08 10 PISO P32C32 32 32 80 08 20 PISO P8R8 8 isolated D I 8 220V relay 80 08 30 PISO P8SSR8AC 8 isolated D I 8 SSR AC 80 08 30 PISO P8SSR8DC 8 isolated D I 8 SSR DC 80 08 30 PISO 730 16 DI 16 D O 16 isolated D I 16 isolated D O ...

Page 22: ... ISO cards installed in this PC printf n for i 0 i wBoards i PIO_GetConfigAddressSpace i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice printf nCard_ d wBase x wIrq x subID x x x SlotID x x i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice printf ShowPioPiso wSubVendor wSubDevice wSubAux Find all PIO D144 in this PC Step1 Detect all PIO D144 cards first wSubVendor 0x80...

Page 23: ...rd directly Find the configure address space of PIO_D144 Step1 Detect all PIO D144 cards first wSubVendor 0x80 wSubDevice 0x01 wSubAux 0x00 for PIO D144 wRetVal PIO_DriverInit wBoards wSubVendor wSubDevice wSubAux printf Threr are d PIO D144 Cards in this PC n wBoards Step2 Save resource of all PIO D144 cards installed in this PC for i 0 i wBoards i PIO_GetConfigAddressSpace i wBase wIrq t1 t2 t3 ...

Page 24: ...program is given as follows wRetVal PIO_DriverInit wBoards 0xff 0xff 0xff find all PIO_PISO series card printf nThrer are d PIO_PISO Cards in this PC wBoards if wBoards 0 exit 0 printf n for i 0 i wBoards i PIO_GetConfigAddressSpace i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice printf nCard_ d wBase x wIrq x subID x x x SlotID x x i wBase wIrq wSubVendor wSubDevice wSubAux wSlotB...

Page 25: ...CI_slot1 run PIO_PISO EXE record the wSlotBus1 wSlotDevice1 3 Remove all PIO D144 from this PC 4 Install one PIO D144 into the PC s PCI_slot2 run PIO_PISO EXE record the wSlotBus2 wSlotDevice2 5 Repeat 3 4 for all PCI_slot record all wSlotBus wSlotDevice The records may be as follows PC s PCI slot WslotBus WslotDevice Slot_1 0 0x07 Slot_2 0 0x08 Slot_3 0 0x09 Slot_4 0 0x0A PCI BRIDGE Slot_5 1 0x0A...

Page 26: ...from D I will be the same as D O The operation steps are given as follows 1 Remove all 50 pin flat cable between CN2 and CN3 2 Install all PIO D144 cards into this PC system 3 Power on and run DEM10 EXE 4 Now all D I value will be different from D O value 5 Install a 50 pin flat cable into CN2 CN3 of any PIO D144 card 6 There will be one card s D I value D O value the card number is also show in s...

Page 27: ...rom D I port Write 8 bit data to D O port WBase 0xc4 Reserved Select the active I O port WBase 0xc8 Reserved I O Port 0 5 direction control WBase 0xcc Reserved I O Port 6 11 direction control WBase 0xd0 Reserved I O Port 12 17 direction control Note Refer to Sec 3 1 for more information about wBase 3 3 1 RESET Control Register Read Write wBase 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rese...

Page 28: ...Aux3 Aux2 Aux1 Aux0 Note Refer to Sec 3 1 for more information about wBase When the Aux is used as D O the output state is controlled by this register This register is designed for feature extension so don t control this register now 3 3 4 INT Mask Control Register Read Write wBase 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 CN1_PC3 CN1_PC2 CN1_PC1 CN1_PC0 Note Refer to Sec 3 1 for m...

Page 29: ... Write wBase 0x2A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 CN1_PC3 CN1_PC2 CN1_PC1 CN1_PC0 Note Refer to Sec 3 1 for more information about wBase PC0 0 select the non inverted signal from PC0 of CN1_PC PC0 1 select the inverted signal from PC0 of CN1_PC outp wBase 0x2a 0 select the non inverted input CN1_PC0 1 2 3 outp wBase 0x2a 0x0f select the inverted input of CN1_PC0 1 2 3 outp ...

Page 30: ...d as D I port outp wBase 0xc0 Val write to D O port Val inp wBase 0xc0 read from D I port 3 3 8 Active I O Port Control Register Read Write wBase 0xc4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 Note Refer to Sec 3 1 for more information about wBase There are eighteen 8 bit I O port in the PIO D144 Only one I O port can be active at the same time outp wBase 0xc4 0 I O p...

Page 31: ...ort There are eighteen 8 bit I O port in the PIO D144 Every I O port can be programmed as D I or D O port When the PC is first power on all eighteen ports are used as D I port The I O port location is given as follows Connector of PIO D144 PA0 to PA7 PB0 to PB7 PC0 to PC7 CN1 CN1_PA CN1_PB CN1_PC CN2 CN2_PA CN2_PB CN2_PC CN3 CN3_PA CN3_PB CN3_PC CN4 CN4_PA CN4_PB CN4_PC CN5 CN5_PA CN5_PB CN5_PC CN...

Page 32: ...urce code TC LARGE DEMO demo program source code TC LARGE LIB PIO H library header file TC LARGE LIB PIO C library source file TC LARGE LIB A BAT compiler file TC LARGE LIB B BAT link file TC LARGE LIB PIO LIB library file TC LARGE DEMO1 PIO H library header file TC LARGE DEMO1 DEMO1 C demo1 source file TC LARGE DEMO1 DEMO1 PRJ TC project file TC LARGE DEMO1 IOPORTL LIB I O port library file TC LA...

Page 33: ...e 0x05 define AUX_SR wBase 0x07 define INT_PCR wBase 0x2a define RW_8BitDR wBase 0xc0 define ACT_IOPCR wBase 0xc4 define CN1_PA 0 define CN1_PB 1 define CN1_PC 2 define CN2_PA 3 define CN2_PB 4 define CN2_PC 5 define CN3_PA 6 define CN3_PB 7 define CN3_PC 8 define CN4_PA 9 define CN4_PB 10 define CN4_PC 11 define CN5_PA 12 define CN5_PB 13 define CN5_PC 14 define CN6_PA 15 define CN6_PB 16 define ...

Page 34: ...wIrq x subID x x x SlotID x x i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice select card_0 PIO_GetConfigAddressSpace 0 wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice printf n 3 Card_0 D O test wBase x wBase step 1 make sure which ports are D O ports in this demo only CN1_PA CN1_PB CN1_PC are D O port step 2 enable all D I O port outp wBase 1 enable D I O step 3 sele...

Page 35: ...Base 0xc0 0xaa set CN1_PB 0xaa outp wBase 0xc4 2 select CN1_PC outp wBase 0xc0 0x5a set CN1_PC 0x5a c getch if c Q c q break printf nCN1 PA 0xAA PB 0x55 PC 0xA5 press Q to stop outp wBase 0xc4 0 select CN1_PA outp wBase 0xc0 0xAA set CN1_PA 0xAA outp wBase 0xc4 1 select CN1_PB outp wBase 0xc0 0x55 set CN1_PB 0x55 outp wBase 0xc4 2 select CN1_PC outp wBase 0xc0 0xa5 set CN1_PC 0xA5 c getch if c Q c...

Page 36: ...ubAux wSlotBus wSlotDevice printf nCard_ d wBase x wIrq x subID x x x SlotID x x i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice select card_0 PIO_GetConfigAddressSpace 0 wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice step 1 make sure which ports are D O ports in this demo all D O ports are output port step 2 enable all D I O port outp wBase 1 enable D I O step 3 sel...

Page 37: ... PC3 outp wBase 0xc0 0x10 getch PA4 PB4 PC4 outp wBase 0xc0 0x20 getch PA5 PB5 PC5 outp wBase 0xc0 0x40 getch PA6 PB6 PC6 outp wBase 0xc0 0x80 getch PA7 PB7 PC7 PIO_DriverClose This demo program is designed for CN1 CN6 The user can install a DB 24C into CN1 CN6 of PIO D144 This demo will request the user to input a number K as following If the DB 24C is installed in CN1 key in 0 If the DB 24C is i...

Page 38: ...7 putch 0x07 putch 0x07 printf 1 There are no PIO D144 card in this PC n exit 0 printf n 2 Show the Configuration Space of all PIO D144 for i 0 i wBoards i PIO_GetConfigAddressSpace i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice printf nCard_ d wBase x wIrq x subID x x x SlotID x x i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice select card_0 PIO_GetConfigAddressSp...

Page 39: ..._8259 1 irqmask 0xff 1 wIrq 8 setvect wIrq 8 0x70 irq_service outp wBase 0x2a 0 select the non inverte input now_int_state 0 now int_signal is low outp wBase 5 1 enable interrupt enable void interrupt irq_service if now_int_state 0 COUNT find a high_pulse outp wBase 0x2a 1 select the inverte input now_int_state 1 now int_signal is High else find a low_pulse here outp wBase 0x2a 0 select the non in...

Page 40: ...h 0x07 putch 0x07 printf 1 There are no PIO D144 card in this PC n exit 0 printf n 2 Show the Configuration Space of all PIO D144 for i 0 i wBoards i PIO_GetConfigAddressSpace i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice printf nCard_ d wBase x wIrq x subID x x x SlotID x x i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice select card_0 PIO_GetConfigAddressSpace 0 ...

Page 41: ... A2_8259 1 irqmask 0xff 1 wIrq 8 setvect wIrq 8 0x70 irq_service outp wBase 5 1 enable interrupt now_int_state 1 now int_signal is low outp wBase 0x2a 1 select the inverte input enable void interrupt irq_service if now_int_state 0 find a high_pulse here outp wBase 0x2a 1 select the inverte input now_int_state 1 now int_signal is High else COUNT find a low_pulse outp wBase 0x2a 0 select the non inv...

Page 42: ...dwVal clrscr PIO_DriverInit wBoards 0x80 0x01 0x00 printf n 1 Threr are d PIO D144 Cards in this PC wBoards if wBoards 0 putch 0x07 putch 0x07 putch 0x07 printf 1 There are no PIO D144 card in this PC n exit 0 printf n 2 Show the Configuration Space of all PIO D144 for i 0 i wBoards i PIO_GetConfigAddressSpace i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice printf nCard_ d wBase x ...

Page 43: ...A1_8259 1 irqmask 0xff 1 wIrq irqmask inp A2_8259 1 outp A2_8259 1 irqmask 0xff 1 wIrq 8 setvect wIrq 8 0x70 irq_service invert 0x05 outp wBase 0x2a invert CN1_PC0 non inverte input CN1_PC1 inverte input CN1_PC2 non inverte input CN1_PC3 non inverte input now_int_state 0x0a Now CN1_PC0 low CN1_PC1 high CN1_PC2 low CN1_PC3 high CNT_L1 CNT_L2 CNT_L3 CNT_L4 0 low pulse count CNT_H1 CNT_H2 CNT_H3 CNT_...

Page 44: ..._L3 invert invert 4 if int_c 0x08 0 cc new_int_state 0x08 if cc 0 CNT_H4 else CNT_L4 invert invert 8 now_int_state new_int_state outp wBase 0x2a invert if wIrq 8 outp A2_8259 0x20 outp A1_8259 0x20 4 7 DEMO 6 Outport of CN1 CN6 demo 6 D O demo step 1 connect a DB 24C to CN1 of PIO D144 step 2 run DEMO6 EXE step 3 check the LED s of DB 24C will turn on sequentially include PIO H ГК Атлант Инжинирин...

Page 45: ...SubDevice wSubAux wSlotBus wSlotDevice printf n 3 Card_0 D O test wBase x wBase outp D144 Disable Reset DIO of D144 outp D144 Enable outp IO_SCR0 0x00 while 1 printf n for i 1 i 0x80 i i 1 printf nCN1 PA 02xH PB 02xH PC 02xH press Q to stop i i i outp Act_IOPCR CN1_PA outp RW_8BitDR i outp Act_IOPCR CN1_PB outp RW_8BitDR i outp Act_IOPCR CN1_PC outp RW_8BitDR i sleep 1 printf n for i 1 i 0x80 i i ...

Page 46: ... press Q to stop i i i outp Act_IOPCR CN5_PA outp RW_8BitDR i outp Act_IOPCR CN5_PB outp RW_8BitDR i outp Act_IOPCR CN5_PC outp RW_8BitDR i sleep 1 printf n for i 1 i 0x80 i i 1 printf nCN6 PA 02xH PB 02xH PC 02xH press Q to stop i i i outp Act_IOPCR CN6_PA outp RW_8BitDR i outp Act_IOPCR CN6_PB outp RW_8BitDR i outp Act_IOPCR CN6_PC outp RW_8BitDR i sleep 1 if i 0x80 i 0x01 break if kbhit 0 c get...

Page 47: ...144 card in this PC n exit 0 printf n 2 The Configuration Space wBase for i 0 i wBoards i PIO_GetConfigAddressSpace i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice printf nCard_ d wBase x wIrq x subID x x x SlotID x x i wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice PIO_GetConfigAddressSpace 0 wBase wIrq wSubVendor wSubDevice wSubAux wSlotBus wSlotDevice for printf n...

Page 48: ... read CN3_PA if val 0x55 ok 0 outp wBase 0xc4 3 select CN2_PA outp wBase 0xc0 0xAA CN2_PA 0xAA outp wBase 0xc4 6 select CN3_PA val inp wBase 0xc0 0xff read CN3_PA if val 0xaa ok 0 printf nCard Number d wBase x card wBase if ok 1 printf Test OK else printf Test ERROR delay_ms int t int i j k l m for i 0 i t i for j 0 j 100 j m 0 for k 0 k 100 k l j t i m l ГК Атлант Инжиниринг официальный представи...

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