3.2.2.4 The status register
Address
10h
is used by the status register. Reading from this
address will get the data from the status register. The format of status
register is:
Bit7-6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Gain
Control
8245
Timer 1
8245
Timer 0
8245
Timer 2
Reserve
d
Analog
input
type
A/D Busy
Bit 7-6: Current A/D gain control.
Bit 5 : Output of 8254 timer 1.
Bit 4 : Output of 8254 timer 0.
Bit 3 : Output of 8254 timer 2.
Bit 2 : Reserved. Used for hardware testing.
Bit 1 : Analog input type, ‘1’ indicated that analog input type is
single-ended and ‘0’ indicated analog input is differential.
Bit 0 : The A/D busy signal. ‘0’ indicates busy, A/D is under
conversion. ‘1’ indicates not busy, A/D is completely
converted and is idle now.
3.2.2.5 The A/D software trigger register
Writing to this port (
1Ch
) will generate an A/D trigger pulse signal.
Note: Although a very fast trigger can be performed (more than the speed
of A/D controller, 125K) via this method, a reasonable delay time
should be left between the two triggers.
A/D
Busy
Software
trigger
8
μ
s
Delay time
Conversion Time
Figure 3-1. Software trigger delay time.
PCI-1002 User’s Manual (Ver. 2.4, Mar./2004, PPH-015-24) ---- 29