ICP DAS USA A-812PG Hardware User Manual Download Page 15 | Manualshive

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ICP DAS USA A-812PG Hardware User Manual Download Page 15

2.3.7

JP6 : DMA DACK Selection,

JP7 : DMA DRQ Selection

The DMA channel cannot be shared.

The A-812PG software driver can support 8

different boards in one PC based system, but only

two of these boards

can use DMA

transfer function.

NO DMA

1

5

2

6

DRQ

JP7

1

5

2

6

DACK

JP8

JP8

JP7

1

5

2

6

DRQ

1

5

2

6

DACK

DMA 1

(default)

1

5

2

6

DRQ

JP7

1

5

2

6

JP8

DACK

DMA 3

A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) -----

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Summary of Contents for A-812PG

Page 1: ...DAS is believed to be accurate and reliable However no responsibility is assumed by ICP DAS for its use nor for any infringements of patents or other rights of third parties resulting from its use Cop...

Page 2: ...________________________________________ 10 2 3 Jumper Setting __________________________________________________________ 11 2 3 1 JP3 D A Internal Reference Voltage Selection_________________________...

Page 3: ...______________________________________ 31 2 9 Analog Input Signal Connection ____________________________________________ 32 2 10 Pin Assignment________________________________________________________...

Page 4: ...gital input 16 channels of TTL compatible digital output and one 16 bit counter timer channel for timing input and output 1 2 Features The maximum sample rate of A D converter is about 62 5 K sample s...

Page 5: ...V 0 3125V input range 10V or 0 3125V by Jumper JP4 selected Input current 250 nA max 125 nA typical at 25 deg On chip sample and hold Over voltage continuous single channel to 70Vp p Input impedance 1...

Page 6: ...AC or DC reference input Maximum output limit 10V Output drive 5mA Settling time 0 6 microseconds to 0 01 for full scale step 1 3 5 Digital I O Output port 16 bits TTL compatible Input port 16 bits T...

Page 7: ...0 to implement a machine independent timer Clock input frequency DC to 10 MHz Pacer output 0 00047Hz to 0 5MHz Input gate TTL compatible Internal Clock 2M Hz 1 3 8 Direct Memory Access Channel DMA Lev...

Page 8: ...st In addition to this manual the package includes the following items A 812PG multifunction card A 812PG utility diskette A 812PG DOS software manual Attention If any of these items is missing or dam...

Page 9: ...ardware Configuration 2 1 Board Layout A 812PG ISA BUS ISA BUS CN5 CN4 JP5 SW1 CN2 JP4 JP 8 JP7 JP6 JP1 JP3 CN3 CN1 BB ADS 774 JP2 JP 9 VR 1 2 3 4 5 A 812PG Hardware Manual Ver 1 2 Sep 2005 IPH 004 12...

Page 10: ...address is 0x220 ON 1 2 3 4 5 6 A9 A8 A7 A6 A5 A4 SW1 BASE ADDRESS BASE ADDR A9 A8 A7 A6 A5 A4 200 20F OFF ON ON ON ON ON 210 21F OFF ON ON ON ON OFF 220 22F OFF ON ON ON OFF ON 230 23F OFF ON ON ON...

Page 11: ...E0 2E7 AT GPIB 3D0 3DF CGA 2E8 2EF Serial Port 3E8 3EF Serial Port 2F8 2FF Serial Port 3F0 3F7 Floppy Disk 300 31F Prototype Card 3F8 3FF Serial Port 2 3 Jumper Setting 2 3 1 JP3 D A Internal Referenc...

Page 12: ...ltage the D A output voltage may be AC 10V 2 3 3 JP8 A D Trigger Source Selection Ch 1 INT Ch 2 INT default JP1 2 vref Ch 1 EXT ExtRef1 Ch 2 EXT ExtRef2 Ch 1 INT Ch 2 EXT ExtRef2 JP1 2 vref Ch 1 EXT E...

Page 13: ...to 10V total channel 2 3 5 JP5 Interrupt Level Selection The interrupt channel can not be shared The A 812PG software driver can support 8 different boards in one system but only 2 of these cards can...

Page 14: ...clock ExtCLK CN3 pin 8 The block diagram is given in section 2 6 The clock source must be very stable It is recommended to use internal 2M clock The A 812PG software driver uses the counter0 as a mach...

Page 15: ...e driver can support 8 different boards in one PC based system but only two of these boards can use DMA transfer function NO DMA 1 5 2 6 DRQ JP7 1 5 2 6 DACK JP8 JP8 JP7 1 5 2 6 DRQ 1 5 2 6 DACK DMA 1...

Page 16: ...Base 4 A D Low Byte D A Channel 0 Low Byte Base 5 A D High Byte D A Channel 0 High Byte Base 6 DI Low Byte D A Channel 1 Low Byte Base 7 DI High Byte D A Channel 1 High Byte Base 8 Reserved A D Clear...

Page 17: ...se 4 A D Low Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 READ Base 5 A D High Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 READY...

Page 18: ...ital data to analog output The low 8 bits of D A channel 1 are stored in address BASE 4 and high 4 bits are stored in address BASE 5 The address BASE 6 and BASE 7 store the 12 bits data for D A channe...

Page 19: ...high 8 bits are stored in address BASE 7 2 4 5 Clear Interrupt Request WRITE Base 8 Clear Interrupt Request Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X X don t care XXXXXXX...

Page 20: ...control code The software driver does not take care the gain settling time so the user need to delay the gain settling time if gain changed If the application program need to run in different machine...

Page 21: ...gnals D3 D0 select the active channel 2 4 8 A D Mode Control Register WRITE Base B A D Mode Control Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X D2 D1 D0 X don t care JP8...

Page 22: ...it until the ready bit is 0 The pacer trigger can control the sampling rate very precisely So the converted data can be used to reconstruct the waveform of analog input signal In pacer trigger mode th...

Page 23: ...version operation The address BASE 5 offers a ready bit to indicate an A D conversion complete The software driver uses this control word to detect the A 812PG hardware board The software initiates a...

Page 24: ...e E D O Output Latch High Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D15 D14 D13 D12 D11 D10 D9 D8 D O 16 bits output data D15 D0 D15 MSB D0 LSB The A 812PG provides 16 TTL compa...

Page 25: ...w A 812PG Output Latch Register Output Latch Register Latch Reset Power on reset Reset Latch D0 D7 D8 D15 CN5 1 8 9 16 TTL DI DGND 17 18 DGND D0 D7 Base D Base E External Device A 812PG Read Read D0 D...

Page 26: ...iagram is as below Cin clock input Cout clock output INTCLK internal clock CN3 connector CN3 Cin Gate Cout Counter 0 Cin Gate Cout Counter 1 Cin Gate Cout Counter 2 4M 2M INTCLK VCC 10K CN3 Pin 8 PACE...

Page 27: ...ontrol register BASE 9 select gain A D multiplex control register BASE A select analog input A D mode control register BASE B select trigger type and transfer type A D software trigger control registe...

Page 28: ...are the settling time the user should delay enough settling time if switching from one channel to next channel The gain control module also need settling time if gain control code changed Because the...

Page 29: ...is mode can be used with all trigger modes The software scans A D high byte data register BASE 5 until READY_BIT 0 The low byte data is also ready in BASE 4 2 Interrupt transfer This mode can be used...

Page 30: ...er software trigger polling transfer 2 Sends channel number to multiplexer control register 3 Sends the gain control code value to gain control register 4 Delays the settling time 5 Sends any value to...

Page 31: ...ence voltage can be AC DC 10V The block diagram is given as below A 812PG D A channel 0 Base 4 5 Ref JP1 JP2 JP3 5 10 V Internal Reference D A channel 1 D0 D7 Base 6 7 Ref 13 17 15 2 4 20 Analog Gnd V...

Page 32: ...2 9 Analog Input Signal Connection FG1 Connecting analog input configuration A D CH0 AGND Es A 812PG A D CHn A 812PG Hardware Manual Ver 1 2 Sep 2005 IPH 004 12 32...

Page 33: ...2 10 Pin Assignment A 812PG Hardware Manual Ver 1 2 Sep 2005 IPH 004 12 33...

Page 34: ...16 channel isolated digital input board The A 812PG provides 16 channel non isolated TTL compatible digital inputs from CN4 If connecting to DB 16P the A 812PG can provide 16 channels isolated digita...

Page 35: ...Before calibrating the A 812PG user should take care the following issue One 6 digit multi meter DVM One stable voltage source 4 9988V Diagnostic program A812DIAG EXE this program included in the deli...

Page 36: ...all seven VRs VR Num Description VR1 D A channel 0 s gain adjustment VR2 D A channel 1 s gain adjustment VR3 A D s gain adjustment VR4 A D s Amplifier offset adjustment VR5 A D s offset adjustment Fi...

Page 37: ...DVM 4 9988V 9 Press Enter key 3 3 A D Calibration Steps 1 Refer Fig3 2 wiring diagnostics 2 Run A812DIAG exe 3 Press Enter key until A D calibration start 4 Adjust VR5 until shower 4094 4095 5 Press...

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