3 - 4
The FM detector outputs “FMNL” signal from IC1001, pin 14
is applied to the CPU (LOGIC unit; IC101, pin 94) to control
the noise squelch level.
(3) AM DEMODULATOR CIRCUIT
The AM demodulater circuit (IC2001) has the envelope
detect function and the synchronous detect function.
An AM detector (IC2001) demodulates the AM signal into an
AF signal. The 3rd IF signal from the IF amplifier (Q911) is
amplified at the buffer amplifier (Q1031), and is then applied
to the AM demodulater circuit (IC2001)to demodulate the 3rd
IF signal into the AM AF signal. The AF signal which is the
AM envelope detect the AF signal or the AM synchronous
detect AF signal passes through the AF input mode selector
switch (IC1201).
3-1-10 AF INPUT MODE SELECTOR SWITCH
(MAIN AND LOGIC UNITS)
The AF input mode selector switch (MAIN unit; IC1201) con-
sists of 4 analog switches. The switches are selected mode
signals of “AFS1” and “AFS2” from the CPU (LOGIC unit;
IC101) via the shift registor (MAIN unit; IC1601), and are
selected by the squelch control signal from the CPU (LOGIC
unit; IC101). The AF signal is output from IC1201 (MAIN unit;
pin 13).
3-1-11 AF AMPLIFIER CIRCUIT
(MAIN AND FRONT UNITS)
The AF signal output is passed though the low-pass filter
(IC1211) to suppress unwanted signals. The filtered signal is
mixed with “BEEP” signal at the AF level variable circuit
(MAIN unit; IC1251), and is then applied to the AF amplifier
circuit and the AF level variable circuit (IC1251).
The AF level variable circuit controls the AF level by the “AF
GAIN” (R141) on the VR BOARD. The AF signal is applied to
the AF mute circuit to suppress the noise when “AF GAIN”
(R141) level is minimum, and is then power-amplified at
IC1291 on the MAIN unit to drive the speaker.
The one of the AF amplified signal is output “AAFO” signal to
record the AF signal to the AF recording jack (PLL unit; J3).
3-1-12 AGC AND S-METER CIRCUITS (MAIN UNIT)
The AGC (Automatic Gain Control) circuit reduces signal fad-
ing and keep the audio output level constant. The receiver
gain is determined by voltage on the AGC line (Q1063, col-
lector). When strong signals are received, the AGC circuit
decreases the voltage on this line.
The 3rd IF signal is amplified at the IF amplifier (Q911). A por-
tion of the 3rd IF signal is applied to the buffer amplifier
(Q1031) to convert the impedance. The amplified IF signal is
detected at the AGC detector (D1061) via the C1061, and
enters the base of the AGC amplifier (Q1063) to control the
voltage on the AGC line.
The AGC mode is selected by the receiver mode or AGC
swtich on the front panel using the delay control circuit
(Q1064–Q1066). The MDAT signal from the CPU (LOGIC
board; IC101, pin 21) is applied to the shift resistor (IC1601,
pin 2) to produce the AGSS and the AGFS signals. The
AGSS signal is applied to the Q1064, the AGFS signal is
applied to the Q1065, the AGRS signal from the CPU
(LOGIC unit; IC101, pin 80) is applied to the Q1066 to con-
trol the delay control circuit.
The AGRS signal resets the AGC circuit when IC-R75 is
working the memory scaning.
When the AGC switch is selected “OFF”, the Q1061 do not
supply the voltage to the AGC amplifier (Q1063) via the
“AGOS” line, determining the time constant to deactivate the
AGC circuit.
A portion of the AGC bias voltage is amplified at the S-Meter
amplifier circuit (IC1211C, D831), and then applied to the
CPU (LOGIC unit; IC101, pin 95) via the “SML” line. Thus,
the CPU controls S-Meter display.
3-1-13 SQUELCH CIRCUIT
(MAIN AND LOGIC UNIT)
The “SML” signal is applied to the CPU (LOGIC unit; IC101,
pin 91) from the meter amplifier circuit (IC1211C, D831). The
CPU compares “SML” signal with the level of SQL volume on
the VR BOARD to control the “SQL” signal.
The CPU is output the “SQLS” signal from pin 81, and then
applied to the AF selector circuit (MAIN unit; IC1201, pin 6)
which has also the squelch gate circuit.
3-2 PLL CIRCUITS
3-2-1 GENERAL DESCRIPTION
The PLL unit generates a 1st LO signal (69.0415–129.0115
MHz variable), 2nd LO signal (60 MHz), 3rd LO signal
(9.4665 MHz) and BFO signal (455 kHz) used in the MAIN
unit.
The IC-R75 uses a DDS (Direct Digital synthesizer) system.
The DDS system provides rapid lockup time and high quality
frequency oscillation.
3-2-2 REFERENCE OSCILLATOR CIRCUIT
(PLL CIRCUIT)
The 30 MHz reference oscillator circuit consists of X1 and
Q1. The 30 MHz reference frequency is oscillated to produce
all of the LO signals.
3-2-3 1ST LO CIRCUIT (PLL AND MAIN UNIT)
The 30 MHz reference frequency is applied to the DDS-IC
(PLL unit; IC21, pin 40) to oscillate the 1st LO signal. The
reference frequency is compared to the DDS output signal
(PLL unit; IC21, pin 46) to oscillate the PLL lock voltage. The
PLL lock voltage controlls the oscillate frequency of the
VCO1 and VCO2 circuit.
