3 - 3
The comparator outputs “High” when the integrated signals
exceed the reference voltage. C269, R310 and R780 are
used as a time constant circuit. The resulting signal output
from IC22a is inverted at Q46 and is then applied to the
CPU as the “SQLS” signal. The CPU controls the squelch
gate (IC12a) when the “SQLS” signal is received.
(2) S-METER SQUELCH
The S-meter signal from IC19b is applied to the squelch
comparator (IC19a) to close or open the squelch circuit.
The reference voltage is adjusted by R257 and then
applied to the (–) terminal of the comparator (IC19a). When
the S-meter signal exceeds the reference voltage, the com-
parator outputs “High” to the CPU via IC22a and Q46 in the
same manner as the voice activated squelch circuit.
3-2 TRANSMITTER CIRCUITS
3-2-1 MICROPHONE AMPLIFIER CIRCUIT
(LOGIC BOARD)
The AF signals from the [MICROPHONE] connector are
pass through the AF amplifier (IC2008a), and are applied
to the balanced modulator (MAIN unit; IC9, pin 1) via the
AF switch (IC38b). The microphone AGC circuit (D2008,
D2009, Q2009) controls the amplifier gain to prevent signal
distortion.
External modulation inputs from the ACC, NBDP, DSC
sockets or a 2-tone emergency signal from the CPU are
applied to the balanced modulator directly via AF switches
(IC37–IC39).
3-2-2 MODULATION CIRCUIT (MAIN UNIT)
(1) J3E AND J2B MODES
The balanced modulator is used for J3E and J2B modes to
add the audio signal to the BFO frequency, and outputs the
IF signal while suppressing the BFO signal.
The AF signals from the microphone amplifier or external
audio from the modulation terminals are applied to the bal-
anced modulator (IC9, pin 1). The BFO signal from the PLL
unit is applied to (IC9, pin 10) as a carrier signal. A double
sideband signal is output from IC9 (pin 6), and is then
applied to the 9 MHz filter (FI2) to create an SSB signal.
R238 adjusts the balanced level of IC9 for maximum carrier
suppression. In J2B mode, the BFO frequency is shifted
1.7 kHz to set the transmit frequency the same as the dis-
played frequency.
The SSB signal from FI2 is amplified at the 9 MHz amplifi-
ers (Q17–Q19) and is then applied to the mixer circuit (D52).
The switching diode (D19) is turned ON when R8 voltage
disappears.
(2) H3E AND R3E MODES
An SSB signal is applied to the IF amplifier (Q18) in the
same manner as with J3E/J2B mode. The BFO signal from
the PLL unit is amplified at the buffer amplifier (Q30) and is
then applied to the IF amplifier (Q18) as a carrier signal to
be added to an SSB signal. R211 and R212 adjust the car-
rier levels in H3E and R3E modes, respectively.
(3) A1A AND F1B MODES
The CW8 or FSK8 voltage are applied to the balanced
modulator (IC9, pin 4) to upset the balance and create a
carrier signal.
In A1A mode, the CW keying circuit (IC18a) controls
the bias voltage of the IF amplifiers (Q18, Q19) and T/R
switching diode (D19) to switch the carrier transmission.
In F1B mode, BFO frequency is shifted in the PLL unit to
create the mark and space frequencies.
3-2-3 1ST MIXER CIRCUIT (MAIN UNIT)
The amplified signal from the IF amplifier (Q17) is mixed
with a 60 MHz LO signal at the 1st mixer circuit (D52) to
produce a 69.0115 MHz IF signal. The mixer is commonly
used with the receiver 2nd mixer.
The 69.0115 MHz IF signal passes through the filter (FI1b)
and is then applied to the 2nd mixer circuit.
3-2-4 2ND MIXER CIRCUIT (MAIN UNIT)
The filtered signal is mixed with a PLL output frequency
(1LO: 69.5155–99.0155 MHz) at the 2nd mixer circuit (Q3,
Q4) to produce an RF signal which is the same frequency
as the displayed one.
3-2-5 RF FILTER CIRCUIT (MAIN UNIT)
The RF signal passes through the low-pass filter (L55, L56,
C89–C93, C620, C628) and is then amplified at the RF
amplifier (Q2).
The amplified signal is applied to one of nine RF filters.
These RF filters are commonly used with the receiver cir-
cuit which consists of eight high-pass filters and one low-
pass filter. The filtered signal is amplified at the RF ampli-
fier (Q1) and is then applied to the PA150W board via J1.
2-tone alarm
ACC(1) socket
NBDP socket
DSC socket
(GMDSS version only)
IC2008a
5
2
2
5
5
6
6
6
1
1
IC38b
IC38a
IC37a
IC39b
IC37b
Balance upset duing CW, FSK,
Modulator
IC9
1
10
6
FI2
BFO from the PLL/PLLA unit (MHz)
J3E, R3E, H3E, J2B: 9.013
A1A:
FSK:
FSK narrow
J2B narrow
During tuning
9.0116
9.0113 (center)
9.0106 (center)
9.0123
9.0115
Crystal
filter
D9
Q19
Q18
CW keying control
(A1A only)
Q17
9.013 MHz carrier
(R3E, H3E only)
Microphone
•
MODULATOR CIRCUIT
